LM3S818-IQN50-C2 Datasheet, PDF (6/569 Pages) Texas Instruments – LM3S818 Microcontroller

Table of Contents
NRND: Not recommended for new designs.
10.2 Signal Description ....................................................................................................... 331
10.3 Functional Description ................................................................................................. 331
10.3.1 Sample Sequencers .................................................................................................... 332
10.3.2 Module Control ............................................................................................................ 332
10.3.3 Hardware Sample Averaging Circuit ............................................................................. 333
10.3.4 Analog-to-Digital Converter .......................................................................................... 333
10.3.5 Differential Sampling ................................................................................................... 334
10.3.6 Test Modes ................................................................................................................. 336
10.3.7 Internal Temperature Sensor ........................................................................................ 336
10.4 Initialization and Configuration ..................................................................................... 337
10.4.1 Module Initialization ..................................................................................................... 337
10.4.2 Sample Sequencer Configuration ................................................................................. 337
10.5 Register Map .............................................................................................................. 338
10.6 Register Descriptions .................................................................................................. 339
11
11.1
11.2
11.3
11.3.1
11.3.2
11.3.3
11.3.4
11.3.5
11.3.6
11.4
11.5
11.6
Universal Asynchronous Receivers/Transmitters (UARTs) ............................. 367
Block Diagram ............................................................................................................ 368
Signal Description ....................................................................................................... 368
Functional Description ................................................................................................. 369
Transmit/Receive Logic ............................................................................................... 369
Baud-Rate Generation ................................................................................................. 369
Data Transmission ...................................................................................................... 370
FIFO Operation ........................................................................................................... 370
Interrupts .................................................................................................................... 371
Loopback Operation .................................................................................................... 372
Initialization and Configuration ..................................................................................... 372
Register Map .............................................................................................................. 373
Register Descriptions .................................................................................................. 374
12 Synchronous Serial Interface (SSI) .................................................................... 407
12.1 Block Diagram ............................................................................................................ 407
12.2 Signal Description ....................................................................................................... 407
12.3 Functional Description ................................................................................................. 408
12.3.1 Bit Rate Generation ..................................................................................................... 408
12.3.2 FIFO Operation ........................................................................................................... 408
12.3.3 Interrupts .................................................................................................................... 409
12.3.4 Frame Formats ........................................................................................................... 409
12.4 Initialization and Configuration ..................................................................................... 417
12.5 Register Map .............................................................................................................. 418
12.6 Register Descriptions .................................................................................................. 419
13 Analog Comparator .............................................................................................. 445
13.1 Block Diagram ............................................................................................................ 445
13.2 Signal Description ....................................................................................................... 445
13.3 Functional Description ................................................................................................. 446
13.3.1 Internal Reference Programming .................................................................................. 447
13.4 Initialization and Configuration ..................................................................................... 448
13.5 Register Map .............................................................................................................. 448
13.6 Register Descriptions .................................................................................................. 449
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June 18, 2012
Texas Instruments-Production Data