LM3S818-IQN50-C2 Datasheet, PDF (11/569 Pages) Texas Instruments – LM3S818 Microcontroller

NRND: Not recommended for new designs.
Stellaris^® LM3S818 Microcontroller
List of Tables
Table 1.
Table 2.
Table 2-1.
Table 2-2.
Table 2-3.
Table 2-4.
Table 2-5.
Table 2-6.
Table 2-7.
Table 2-8.
Table 2-9.
Table 2-10.
Table 2-11.
Table 2-12.
Table 2-13.
Table 3-1.
Table 3-2.
Table 3-3.
Table 3-4.
Table 3-5.
Table 3-6.
Table 3-7.
Table 3-8.
Table 3-9.
Table 4-1.
Table 4-2.
Table 4-3.
Table 5-1.
Table 5-2.
Table 5-3.
Table 5-4.
Table 5-5.
Table 5-6.
Table 6-1.
Table 6-2.
Table 7-1.
Table 7-2.
Table 7-3.
Table 7-4.
Table 7-5.
Table 7-6.
Table 8-1.
Table 8-2.
Table 8-3.
Table 8-4.
Table 9-1.
Revision History .................................................................................................. 20
Documentation Conventions ................................................................................ 25
Summary of Processor Mode, Privilege Level, and Stack Use ................................ 48
Processor Register Map ....................................................................................... 49
PSR Register Combinations ................................................................................. 54
Memory Map ....................................................................................................... 62
Memory Access Behavior ..................................................................................... 64
SRAM Memory Bit-Banding Regions .................................................................... 66
Peripheral Memory Bit-Banding Regions ............................................................... 66
Exception Types .................................................................................................. 72
Interrupts ............................................................................................................ 73
Exception Return Behavior ................................................................................... 77
Faults ................................................................................................................. 78
Fault Status and Fault Address Registers .............................................................. 79
Cortex-M3 Instruction Summary ........................................................................... 81
Core Peripheral Register Regions ......................................................................... 85
Memory Attributes Summary ................................................................................ 88
TEX, S, C, and B Bit Field Encoding ..................................................................... 91
Cache Policy for Memory Attribute Encoding ......................................................... 92
AP Bit Field Encoding .......................................................................................... 92
Memory Region Attributes for Stellaris Microcontrollers .......................................... 92
Peripherals Register Map ..................................................................................... 93
Interrupt Priority Levels ...................................................................................... 112
Example SIZE Field Values ................................................................................ 140
JTAG_SWD_SWO Signals (48QFP) ................................................................... 144
JTAG Port Pins Reset State ............................................................................... 145
JTAG Instruction Register Commands ................................................................. 149
System Control & Clocks Signals (48QFP) .......................................................... 153
Reset Sources ................................................................................................... 154
Clock Source Options ........................................................................................ 158
Possible System Clock Frequencies Using the SYSDIV Field ............................... 159
System Control Register Map ............................................................................. 163
PLL Mode Control .............................................................................................. 176
Flash Protection Policy Combinations ................................................................. 213
Flash Register Map ............................................................................................ 217
GPIO Pins With Non-Zero Reset Values .............................................................. 231
GPIO Pins and Alternate Functions (48QFP) ....................................................... 231
GPIO Signals (48QFP) ....................................................................................... 231
GPIO Pad Configuration Examples ..................................................................... 236
GPIO Interrupt Configuration Example ................................................................ 236
GPIO Register Map ........................................................................................... 237
Available CCP Pins ............................................................................................ 271
General-Purpose Timers Signals (48QFP) ........................................................... 272
16-Bit Timer With Prescaler Configurations ......................................................... 274
Timers Register Map .......................................................................................... 281
Watchdog Timer Register Map ............................................................................ 308
June 18, 2012
11
Texas Instruments-Production Data