LM3S818-IQN50-C2 Datasheet, PDF (236/569 Pages) Texas Instruments – LM3S818 Microcontroller

NRND: Not recommended for new designs.
General-Purpose Input/Outputs (GPIOs)
Table 7-4. GPIO Pad Configuration Examples
Configuration
GPIO Register Bit Value^a
AFSEL DIR
ODR
DEN
Digital Input (GPIO)
0
0
0
1
Digital Output (GPIO)
0
1
0
1
Open Drain Output
0
1
1
1
(GPIO)
Digital Input (Timer
1
X
0
1
CCP)
Digital Input (QEI)
1
X
0
1
Digital Output (PWM)
1
X
0
1
Digital Output (Timer
1
X
0
1
PWM)
Digital Input/Output
1
X
0
1
(SSI)
Digital Input/Output
1
X
0
1
(UART)
Analog Input
(Comparator)
0
0
0
0
Digital Output
(Comparator)
1
X
0
1
a. X=Ignored (don’t care bit)
?=Can be either 0 or 1, depending on the configuration
PUR
?
?
X
?
?
?
?
?
?
0
?
PDR
?
?
X
?
?
?
?
?
?
0
?
DR2R
X
?
?
X
X
?
?
?
?
X
?
DR4R
X
?
?
X
X
?
?
?
?
X
?
DR8R
X
?
?
X
X
?
?
?
?
X
?
SLR
X
?
?
X
X
?
?
?
?
X
?
Table 7-5. GPIO Interrupt Configuration Example
Desired
Pin 2 Bit Value^a
Register
Interrupt
Event
7
6
5
4
Trigger
GPIOIS
0=edge
X
X
X
X
1=level
GPIOIBE
0=single
X
X
X
X
edge
1=both
edges
GPIOIEV 0=Low level,
X
X
X
X
or negative
edge
1=High level,
or positive
edge
GPIOIM
0=masked
0
0
0
0
1=not
masked
a. X=Ignored (don’t care bit)
3
X
X
X
0
2
0
0
1
1
1
X
X
X
0
0
X
X
X
0
7.5 Register Map
Table 7-6 on page 237 lists the GPIO registers. The offset listed is a hexadecimal increment to the
register’s address, relative to that GPIO port’s base address:
236
June 18, 2012
Texas Instruments-Production Data