LM3S818-IQN50-C2 Datasheet, PDF (29/569 Pages) Texas Instruments – LM3S818 Microcontroller

NRND: Not recommended for new designs.
Stellaris^® LM3S818 Microcontroller
■ Internal Memory
– 64 KB single-cycle flash
• User-managed flash block protection on a 2-KB block basis
• User-managed flash data programming
• User-defined and managed flash-protection block
– 8 KB single-cycle SRAM
■ GPIOs
– 0-30 GPIOs, depending on configuration
– 5-V-tolerant in input configuration
– Fast toggle capable of a change every two clock cycles
– Programmable control for GPIO interrupts
• Interrupt generation masking
• Edge-triggered on rising, falling, or both
• Level-sensitive on High or Low values
– Bit masking in both read and write operations through address lines
– Can initiate an ADC sample sequence
– Pins configured as digital inputs are Schmitt-triggered.
– Programmable control for GPIO pad configuration
• Weak pull-up or pull-down resistors
• 2-mA, 4-mA, and 8-mA pad drive for digital communication
• Slew rate control for the 8-mA drive
• Open drain enables
• Digital input enables
■ General-Purpose Timers
– Three General-Purpose Timer Modules (GPTM), each of which provides two 16-bit
timers/counters. Each GPTM can be configured to operate independently:
• As a single 32-bit timer
• As one 32-bit Real-Time Clock (RTC) to event capture
• For Pulse Width Modulation (PWM)
June 18, 2012
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Texas Instruments-Production Data