LM3S818-IQN50-C2 Datasheet, PDF (393/569 Pages) Texas Instruments – LM3S818 Microcontroller

NRND: Not recommended for new designs.
Stellaris^® LM3S818 Microcontroller
Register 12: UART Interrupt Clear (UARTICR), offset 0x044
The UARTICR register is the interrupt clear register. On a write of 1, the corresponding interrupt
(both raw interrupt and masked interrupt, if enabled) is cleared. A write of 0 has no effect.
UART Interrupt Clear (UARTICR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0x044
Type W1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
OEIC
BEIC
PEIC
FEIC
RTIC
TXIC
RXIC
reserved
Type RO
RO
RO
RO
RO
W1C
W1C
W1C
W1C
W1C
W1C
W1C
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:11
10
Name
reserved
OEIC
Type
RO
W1C
Reset
0x00
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Overrun Error Interrupt Clear
The OEIC values are defined as follows:
Value Description
0 No effect on the interrupt.
1 Clears interrupt.
9
BEIC
W1C
0
Break Error Interrupt Clear
The BEIC values are defined as follows:
Value Description
0 No effect on the interrupt.
1 Clears interrupt.
8
PEIC
W1C
0
Parity Error Interrupt Clear
The PEIC values are defined as follows:
Value Description
0 No effect on the interrupt.
1 Clears interrupt.
7
FEIC
W1C
0
Framing Error Interrupt Clear
The FEIC values are defined as follows:
Value Description
0 No effect on the interrupt.
1 Clears interrupt.
June 18, 2012
393
Texas Instruments-Production Data