LM3S818-IQN50-C2 Datasheet, PDF (10/569 Pages) Texas Instruments – LM3S818 Microcontroller

Table of Contents
NRND: Not recommended for new designs.
Figure 12-11. MICROWIRE Frame Format (Continuous Transfer) ............................................. 416
Figure 12-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ............ 417
Figure 13-1. Analog Comparator Module Block Diagram ......................................................... 445
Figure 13-2. Structure of Comparator Unit .............................................................................. 446
Figure 13-3. Comparator Internal Reference Structure ............................................................ 447
Figure 14-1. PWM Unit Diagram ............................................................................................ 458
Figure 14-2. PWM Module Block Diagram .............................................................................. 459
Figure 14-3. PWM Count-Down Mode .................................................................................... 460
Figure 14-4. PWM Count-Up/Down Mode .............................................................................. 461
Figure 14-5. PWM Generation Example In Count-Up/Down Mode ........................................... 461
Figure 14-6. PWM Dead-Band Generator ............................................................................... 462
Figure 15-1. QEI Block Diagram ............................................................................................ 497
Figure 15-2. Quadrature Encoder and Velocity Predivider Operation ........................................ 498
Figure 16-1. 48-Pin QFP Package Pin Diagram ...................................................................... 514
Figure 19-1. Load Conditions ................................................................................................ 527
Figure 19-2. JTAG Test Clock Input Timing ............................................................................. 528
Figure 19-3. JTAG Test Access Port (TAP) Timing .................................................................. 529
Figure 19-4. JTAG TRST Timing ............................................................................................ 529
Figure 19-5. External Reset Timing (RST) .............................................................................. 530
Figure 19-6. Power-On Reset Timing ..................................................................................... 530
Figure 19-7. Brown-Out Reset Timing .................................................................................... 530
Figure 19-8. Software Reset Timing ....................................................................................... 531
Figure 19-9. Watchdog Reset Timing ..................................................................................... 531
Figure 19-10. LDO Reset Timing ............................................................................................. 531
Figure 19-11. ADC Input Equivalency Diagram ......................................................................... 533
Figure 19-12. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing
Measurement .................................................................................................... 534
Figure 19-13. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ................. 534
Figure 19-14. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ..................................... 535
Figure D-1. Stellaris LM3S818 48-Pin LQFP Package ........................................................... 562
Figure D-2. 48-Pin LQFP Tray Dimensions ........................................................................... 564
Figure D-3. 48-Pin LQFP Tape and Reel Dimensions ............................................................. 566
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June 18, 2012
Texas Instruments-Production Data