LM3S818-IQN50-C2 Datasheet, PDF (158/569 Pages) Texas Instruments – LM3S818 Microcontroller

System Control
NRND: Not recommended for new designs.
5.2.3
5.2.4
5.2.4.1
5.2.4.2
3. The internal reset is released and the controller fetches and loads the initial stack pointer, the
initial program counter, the first instruction designated by the program counter, and begins
execution.
The LDO reset timing is shown in Figure 19-10 on page 531.
Power Control
The Stellaris^® microcontroller provides an integrated LDO regulator that is used to provide power
to the majority of the controller's internal logic. For power reduction, the LDO regulator provides
software a mechanism to adjust the regulated value, in small increments (VSTEP), over the range
of 2.25 V to 2.75 V (inclusive)—or 2.5 V ± 10%. The adjustment is made by changing the value of
the VADJ field in the LDO Power Control (LDOPCTL) register.
Clock Control
System control determines the control of clocks in this part.
Fundamental Clock Sources
There are multiple clock sources for use in the device:
■ Internal Oscillator (IOSC). The internal oscillator is an on-chip clock source. It does not require
the use of any external components. The frequency of the internal oscillator is 12 MHz ± 30%.
■ Main Oscillator (MOSC). The main oscillator provides a frequency-accurate clock source by
one of two means: an external single-ended clock source is connected to the OSC0 input pin, or
an external crystal is connected across the OSC0 input and OSC1 output pins. The crystal value
allowed depends on whether the main oscillator is used as the clock reference source to the
PLL. If so, the crystal must be one of the supported frequencies between 3.579545 MHz through
8.192 MHz (inclusive). If the PLL is not being used, the crystal may be any one of the supported
frequencies between 1 MHz and 8.192 MHz. The single-ended clock source range is from DC
through the specified speed of the device. The supported crystals are listed in the XTAL bit field
in the RCC register (see page 173).
The internal system clock (SysClk), is derived from any of the above sources plus two others: the
output of the main internal PLL, and the internal oscillator divided by four (3 MHz ± 30%). The
frequency of the PLL clock reference must be in the range of 3.579545 MHz to 8.192 MHz (inclusive).
Table 5-3 on page 158 shows how the various clock sources can be used in a system.
Table 5-3. Clock Source Options
Clock Source
Drive PLL?
Used as SysClk?
Internal Oscillator (12 MHz) Yes
BYPASS = 0, OSCSRC = 0x1 Yes
BYPASS = 1, OSCSRC = 0x1
Internal Oscillator divide by 4 (3 Yes
MHz)
BYPASS = 0, OSCSRC = 0x2 Yes
BYPASS = 1, OSCSRC = 0x2
Main Oscillator
Yes
BYPASS = 0, OSCSRC = 0x0 Yes
BYPASS = 1, OSCSRC = 0x0
Clock Configuration
Nearly all of the control for the clocks is provided by the Run-Mode Clock Configuration (RCC)
register. This register controls the following clock functionality:
■ Source of clocks in sleep and deep-sleep modes
158
June 18, 2012
Texas Instruments-Production Data