LM3S818-IQN50-C2 Datasheet, PDF (173/569 Pages) Texas Instruments – LM3S818 Microcontroller

NRND: Not recommended for new designs.
Stellaris^® LM3S818 Microcontroller
Register 8: Run-Mode Clock Configuration (RCC), offset 0x060
This register is defined to provide source control and frequency speed.
Run-Mode Clock Configuration (RCC)
Base 0x400F.E000
Offset 0x060
Type R/W, reset 0x078E.3AC0
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
ACG
SYSDIV
USESYSDIV reserved USEPWMDIV
PWMDIV
reserved
Type RO
RO
RO
RO
R/W
R/W
R/W
R/W
R/W
R/W
RO
R/W
R/W
R/W
R/W
RO
Reset
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
PWRDN OEN BYPASS PLLVER
XTAL
OSCSRC
IOSCVER MOSCVER IOSCDIS MOSCDIS
Type RO
Reset
0
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
1
1
1
0
1
0
1
1
0
0
0
0
0
0
Bit/Field
31:28
27
26:23
22
Name
reserved
ACG
SYSDIV
USESYSDIV
Type
RO
R/W
R/W
R/W
Reset
0x0
0
0xF
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Auto Clock Gating
This bit specifies whether the system uses the Sleep-Mode Clock
Gating Control (SCGCn) registers and Deep-Sleep-Mode Clock
Gating Control (DCGCn) registers if the controller enters a Sleep or
Deep-Sleep mode (respectively). If set, the SCGCn or DCGCn registers
are used to control the clocks distributed to the peripherals when the
controller is in a sleep mode. Otherwise, the Run-Mode Clock Gating
Control (RCGCn) registers are used when the controller enters a sleep
mode.
The RCGCn registers are always used to control the clocks in Run
mode.
This allows peripherals to consume less power when the controller is
in a sleep mode and the peripheral is unused.
System Clock Divisor
Specifies which divisor is used to generate the system clock from either
the PLL output or the oscillator source (depending on how the BYPASS
bit in this register is configured). See Table 5-4 on page 159 for bit
encodings.
The PLL VCO frequency is 200 MHz.
If the SYSDIV value is less than MINSYSDIV (see page 184), and the
PLL is being used, then the MINSYSDIV value is used as the divisor.
If the PLL is not being used, the SYSDIV value can be less than
MINSYSDIV.
Enable System Clock Divider
Use the system clock divider as the source for the system clock. The
system clock divider is forced to be used when the PLL is selected as
the source.
If the USERCC2 bit in the RCC2 register is set, then the SYSDIV2 field
in the RCC2 register is used as the system clock divider rather than the
SYSDIV field in this register.
June 18, 2012
173
Texas Instruments-Production Data