LM3S818-IQN50-C2 Datasheet, PDF (42/569 Pages) Texas Instruments – LM3S818 Microcontroller

Architectural Overview
NRND: Not recommended for new designs.
1.4.9
System Block Diagram
Figure 1-2. LM3S818 Controller System-Level Block Diagram
VDD_3.3V
LDO
LDO
VDD_2.5V
GND
ARM Cortex-M3
(50 MHz)
CM3Core
NVIC
DCode
ICode
Flash
(64 KB)
Debug Bus
OSC0
OSC1
RST
IOSC PLL
POR
BOR
System
Control
& Clocks
GPIO Port A
APB Bridge
SRAM
(8 KB)
Watchdog
Timer
GPIO Port B
PA5/SSITx
PA4/SSIRx
PA3/SSIFss
PA2/SSIClk
PA1/U0Tx
PA0/U0Rx
SSI
UART0
GPIO Port C
Analog
Comparator
PWM1
PC3/TDO/SWO
PC2/TDI
PC1/TMS/SWDIO
PC0/TCK/SWCLK
PC7/CCP4
PC5/CCP1
PC4/PhA
PC6/PhB
PE0/PWM4
PE1/PWM5
JTAG
SWD/SWO
GP Timer2
QEI
GPIO Port E
PWM2
GPIO Port D
PWM0
UART1
GP Timer0
GP Timer1
PB7/TRST
PB6/C0+
PB4/C0-
PB5/C0o
PB2/IDX
PB1/PWM3
PB0/PWM2
PB3/Fault
PD0/PWM0
PD1/PWM1
PD2/U1Rx
PD3/U1Tx
PD4/CCP0
PD5/CCP2
ADC5
ADC4
ADC3
ADC2
ADC1
ADC0
LM3S818
ADC
Temperature
Sensor
42
June 18, 2012
Texas Instruments-Production Data