LM3S818-IQN50-C2 Datasheet, PDF (544/569 Pages) Texas Instruments – LM3S818 Microcontroller

Register Quick Reference
NRND: Not recommended for new designs.
31
30
29
28
27
26
25
24
23
22
15
14
13
12
11
10
9
8
7
6
SYSHNDCTRL, type R/W, offset 0xD24, reset 0x0000.0000
SVC
BUSP MEMP USAGEP TICK PNDSV
MON SVCA
FAULTSTAT, type R/W1C, offset 0xD28, reset 0x0000.0000
DIV0 UNALIGN
BFARV
BSTKE BUSTKE IMPRE PRECISE IBUS MMARV
HFAULTSTAT, type R/W1C, offset 0xD2C, reset 0x0000.0000
DBG FORCED
MMADDR, type R/W, offset 0xD34, reset -
FAULTADDR, type R/W, offset 0xD38, reset -
Cortex-M3 Peripherals
Memory Protection Unit (MPU) Registers
Base 0xE000.E000
MPUTYPE, type RO, offset 0xD90, reset 0x0000.0800
ADDR
ADDR
ADDR
ADDR
DREGION
MPUCTRL, type R/W, offset 0xD94, reset 0x0000.0000
MPUNUMBER, type R/W, offset 0xD98, reset 0x0000.0000
MPUBASE, type R/W, offset 0xD9C, reset 0x0000.0000
ADDR
MPUBASE1, type R/W, offset 0xDA4, reset 0x0000.0000
ADDR
MPUBASE2, type R/W, offset 0xDAC, reset 0x0000.0000
ADDR
MPUBASE3, type R/W, offset 0xDB4, reset 0x0000.0000
ADDR
MPUATTR, type R/W, offset 0xDA0, reset 0x0000.0000
XN
AP
SRD
MPUATTR1, type R/W, offset 0xDA8, reset 0x0000.0000
XN
AP
SRD
MPUATTR2, type R/W, offset 0xDB0, reset 0x0000.0000
XN
AP
SRD
MPUATTR3, type R/W, offset 0xDB8, reset 0x0000.0000
XN
AP
SRD
ADDR
ADDR
ADDR
ADDR
21
20
19
18
17
16
5
4
3
2
1
0
USGA
USAGE
BUS
BUSA
MEM
MEMA
NOCP INVPC INVSTAT UNDEF
MSTKE MUSTKE
DERR IERR
VECT
IREGION
SEPARATE
PRIVDEFEN HFNMIENA ENABLE
NUMBER
VALID
REGION
VALID
REGION
VALID
REGION
VALID
TEX
SIZE
TEX
SIZE
TEX
SIZE
TEX
SIZE
REGION
S
C
B
ENABLE
S
C
B
ENABLE
S
C
B
ENABLE
S
C
B
ENABLE
544
June 18, 2012
Texas Instruments-Production Data