LM3S818-IQN50-C2 Datasheet, PDF (547/569 Pages) Texas Instruments – LM3S818 Microcontroller

NRND: Not recommended for new designs.
Stellaris^® LM3S818 Microcontroller
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30
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15
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7
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5
FCRIS, type RO, offset 0x00C, reset 0x0000.0000
FCIM, type R/W, offset 0x010, reset 0x0000.0000
FCMISC, type R/W1C, offset 0x014, reset 0x0000.0000
Internal Memory
Flash Memory Protection Registers (System Control Offset)
Base 0x400F.E000
USECRL, type R/W, offset 0x140, reset 0x31
FMPRE, type R/W, offset 0x130, reset 0xBFFF.FFFF
DBG
FMPPE, type R/W, offset 0x134, reset 0xFFFF.FFFF
General-Purpose Input/Outputs (GPIOs)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIODATA, type R/W, offset 0x000, reset 0x0000.0000 (see page 239)
READ_ENABLE
READ_ENABLE
PROG_ENABLE
PROG_ENABLE
GPIODIR, type R/W, offset 0x400, reset 0x0000.0000 (see page 240)
GPIOIS, type R/W, offset 0x404, reset 0x0000.0000 (see page 241)
GPIOIBE, type R/W, offset 0x408, reset 0x0000.0000 (see page 242)
GPIOIEV, type R/W, offset 0x40C, reset 0x0000.0000 (see page 243)
GPIOIM, type R/W, offset 0x410, reset 0x0000.0000 (see page 244)
GPIORIS, type RO, offset 0x414, reset 0x0000.0000 (see page 245)
GPIOMIS, type RO, offset 0x418, reset 0x0000.0000 (see page 246)
GPIOICR, type W1C, offset 0x41C, reset 0x0000.0000 (see page 247)
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19
4
3
USEC
DATA
DIR
IS
IBE
IEV
IME
RIS
MIS
IC
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16
2
1
0
PRIS
ARIS
PMASK AMASK
PMISC AMISC
June 18, 2012
547
Texas Instruments-Production Data