LM3S818-IQN50-C2 Datasheet, PDF (100/569 Pages) Texas Instruments – LM3S818 Microcontroller

Cortex-M3 Peripherals
NRND: Not recommended for new designs.
Register 5: Interrupt 0-29 Clear Enable (DIS0), offset 0x180
Note: This register can only be accessed from privileged mode.
The DIS0 register disables interrupts. Bit 0 corresponds to Interrupt 0; bit 29 corresponds to Interrupt
29.
See Table 2-9 on page 73 for interrupt assignments.
Interrupt 0-29 Clear Enable (DIS0)
Base 0xE000.E000
Offset 0x180
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
INT
Type RO
Reset
0
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
INT
Type R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:30
29:0
Name
reserved
INT
Type
Reset Description
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
R/W 0x000.0000 Interrupt Disable
Value Description
0 On a read, indicates the interrupt is disabled.
On a write, no effect.
1 On a read, indicates the interrupt is enabled.
On a write, clears the corresponding INT[n] bit in the EN0
register, disabling interrupt [n].
100
June 18, 2012
Texas Instruments-Production Data