LAN83C175 Datasheet, PDF (68/92 Pages) SMSC Corporation – Ethernet CARDBUS Integrated Controller With Modem Support

Physical Connection
The number of address bits attached to the
modem or external memory is defined by the
user.
Note: nRESETM is active low at power up, and
can be set by a write to a register within the
EPIC/C. RDYM and RINGIN are status bits that
can be read from a register within the EPIC/C.
IREQM is an interrupt request register that,
when active, will drive an interrupt onto the
CardBus interface. This is a maskable interrupt.
The MPWRDWN signal is active high at
initialization, and can be driven low by a write to
a register within the EPIC/C. AUDIOIN goes
straight through the EPIC/C to the CardBus pin
CAUDIO. The audio signal must be in a digital
format. RINGOUT will be high when
MPWRDWN is low, but the modem is still in
reset.
Modem and RAM Access Timing
During a write access to the modem, the timing
on the address, data, chip select, and write
pulse are as shown in figure 21. Writes to the
external RAM have similar timing, with the
option to increase the setup time. Note that the
timings are affected by the settings in the
MDM_ACS_DLY and MDM_XTND_SETUP bits
explained in the NVCTL_m Register Definition.
During a read access from the modem, the
timing on the address, data, chip select, and
read pulse are as shown in figure 22. Access to
the external RAM has similar timing, with the
option to increase access times.
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