LAN83C175 Datasheet, PDF (42/92 Pages) SMSC Corporation – Ethernet CARDBUS Integrated Controller With Modem Support

11 - PHYPWRDWN_N: This bit controls the
nPHYPWRDWN output signal that is used to
control a powerdown signal to the physical
layer. Upon reset, it will be zero, and will then
reflect the value loaded into it during eerecall.
10 - EN_FBTB: This enables fast back to back
operations to the LAN83C175. Note that fast
back to back operations will not work when
writing data to the flash ram.
9 - MODEM_EN: This bit determines whether
modem functionality is enabled. If this bit is
low, the modem cannot be seen from the host.
The modem configuration registers are not
visible, nor can the modem be read from or
written to.
8 - ROMWR_EN: This bit enables or disables
the ability to write to the external flash rom. It
must be high to enable writing.
7 - ROMSPEED: This bit must be set to 0 to
accommodate ROM with a 200 ns access
speed. A 1 accommodates at 120 ns access
speed.
6 - STATUSREG_EN: This bit determines
whether the cardbus function registers are
used for logging interrupts. This bit can be
used to determine whether an interrupt from
the modem is logged and must be explicitly
cleared by a driver through the cardbus
function registers, if statusreg_en is active, or
whether the interrupt line to the host reflects
the interrupt line to the LAN83C175 from the
modem, if statusreg_en is inactive. It must be
set to 1 to be able to write to and read from
the function registers for both the ethernet and
modem functions.
5 - GENERAL PURPOSE I/O[2]: This bit
controls the value of the GPIO[2] pin when
used as an output. When read, this bit always
returns the external value on GPIO[2].
4 - GENERAL PURPOSE I/O[1]: This bit controls
the value of the GPIO[1] pin when used as an
output. When read, this bit always returns the
external value on GPIO[1].
3 - GENERAL PURPOSE OUTPUT ENABLE[2]:
When set, GPIO[2] is driven by the EPIC/C. When
cleared, GPIO[2] is tri-stated and may be used as
an input.
2 - GENERAL PURPOSE OUTPUT ENABLE[1]:
When set, GPIO[1] is driven by the EPIC/C.
When cleared, GPIO[1] is tri-stated and may be
used as an input.
1 - CLOCK RUN SUPPORTED: This bit enables
the EPIC/C to perform the CardBus clock run
function. When set, the clock run function is
enabled. When cleared, the nCLKRUN output is
tri-stated. This bit is only writable in register test
mode. In normal operation, it should only be
changed by re-programming the EEPROM and
resetting the system (hard reset).
0 - ENABLE MEMORY MAP: This bit controls
whether or not the EPIC/C control registers are
visible in memory space. When set, the EPIC/C
control registers will be mapped into I/O space
and memory space (for host systems that do not
have I/O space). When cleared, the control
registers will only be mapped into I/O space. This
bit controls how the host system maps the control
registers at power up by changing the appearance
of the memory base address register in CardBus
configuration space. This bit is only writable in
register test mode. In normal operation, it should
only be changed by re-programming the
EEPROM and resetting the system (hard reset).
Default is disabled when EEPROM recall is
bypassed.
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