LAN83C175 Datasheet, PDF (60/92 Pages) SMSC Corporation – Ethernet CARDBUS Integrated Controller With Modem Support

CardBus CONFIGURATION REGISTERS
00 - DEVICE ID/VENDOR ID
31 through 16 - DEVICE ID: This read only
field returns the LAN83C175 device ID
(0006h). Bit 31 is assigned a value to indicate
SMSC System Products Division vs.
Components Division (0 = System Products, 1
= Components). The remaining bits are
assigned arbitrarily to uniquely identify each
System Products CardBus device.
15 through 0 - VENDOR ID: This read only
field returns the SMSC Vendor ID (10B8h).
04 - CardBus STATUS / COMMAND
Reset Value: 0000000010000000
Bits in this register are set internally by the
LAN83C175. Bits are cleared by writing a 1 to
their respective locations. Writing 0 to a bit
has no effect (in register test mode writing 0
sets the bit).
31 - DETECTED PARITY ERROR: This bit is
set whenever the LAN83C175 detects a parity
error, even if parity error handling is disabled.
30 - SIGNALLED SYSTEM ERROR: This bit
is et whenever the LAN83C175 asserts system
error. The LAN83C175 asserts system error
when an address parity error is detected and
both the nSERR enable and Parity Error
Response bits are set.
29 - RECEIVED MASTER ABORT: This bit is
set whenever an LAN83C175 bus master
transaction is terminated with master-abort.
28 - RECEIVED TARGET ABORT: This bit is
set whenever an LAN83C175 bus master
transaction is terminated with target-abort.
27 - SIGNALLED TARGET ABORT: This bit is
not implemented because the LAN83C175 never
signals target-abort (always returns 0).
26 and 25 - DEVSEL TIMING: These two read
only bits always return "00" to indicate that the
LAN83C175 always asserts DEVSEL with fast
timing (zero wait states).
24 - DATA PARITY DETECTED: This bit is set
whenever the following three conditions are met:
1) the LAN83C175 is acting as bus master on
the CardBus bus; 2) the LAN83C175 asserts
nPERR or observes nPERR asserted; 3) the
Parity Error Response bit is set.
23 - FAST BACK-TO-BACK CAPABLE: This read
only bit always returns 1 to indicate that the
LAN83C175 is capable of accepting fast back-to-
back transactions when the transactions are not
to the same agent.
22 - UDF SUPPORTED: This read only bit tells
the host system whether or not the LAN83C175
supports user definable features. The value of this
bit is recalled from EEPROM at power up and
stored in the NVCTL register. This bit should be
programmed to zero in the EEPROM to indicate
that the LAN83C175 does not support user
definable features.
21 - 66 MHz CAPABLE: This bit always returns
zero to indicate that the LAN83C175 is not 66
MHz capable.
20 through 16: Reserved (always return 0).
COMMAND REGISTER (Lower Word)
Reset Value: 0000000000000000
15 through 10: Reserved (always return 0).
9 - FAST BACK-TO-BACK ENABLE: This bit is
not implemented because the LAN83C175 never
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