LAN83C175 Datasheet, PDF (53/92 Pages) SMSC Corporation – Ethernet CARDBUS Integrated Controller With Modem Support

5 - BROADCAST ADDRESS RECOGNIZED:
This bit is set when a broadcast address has
been recognized.
4 - MULTICAST ADDRESS RECOGNIZED:
This bit is set when a multicast address which
passes the hash filter has been recognized.
3 - MISSED PACKET: This bit is set when a
packet with a recognized address and without
errors (or with masked errors) is not buffered
because the device is in monitor mode. This
bit is also set when the packet overflows the
receive buffer space and cannot be received.
Always returns 0.
2 - CRC ERROR: This bit is set when a
frame's computed CRC does not match the
CRC appended to the frame. If the frame is a
runt, this bit will be clear. In MII mode, this bit
will also be set if receive error was asserted on
the MII interface during reception of the frame.
1 - FRAME ALIGNMENT ERROR: This bit is
set if a CRC error has occurred and the frame
is not byte aligned.
0 - PACKET RECEIVED INTACT: This bit is
set when a packet is received into the buffer
space without error.
A8 - RECEIVE RAM BUFFER
Reset Value: xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
31 through 0 - The receive ram can be read and
written through this I/O port (for test purposes
only). The read or write will occur at the address
specified in the PRLCAR register. The PRLCAR
register will be incremented by four (one dword)
each time this port is read or written.
AC - RECEIVE MTU CURRENT ADDRESS
Reset Value: 1000000000000000
This register contains the receive MTU’s pointer to
the next location it will write in the local receive
ram. The register contains the dword address
and is write only. Reads to this register return
unknown data.
31 through 16 - Unused.
15 through 0 - Address.
B0 - CardBus RECEIVE COPY THRESHOLD
Reset Value: 11111111XX
This register is programmed with the CardBus
receive copy threshold for the LAN83C175. An
early receive warning interrupt will be generated
for each frame after the number of bytes
specified in this register have been copied into
the receive data buffers in host memory. Bits 1
and 0 are ignored, so the granularity of the
threshold is four bytes. The register should only
be written at initialization time.
31 through 11: Unused.
9 through 2: Threshold.
1 and 0: Not writable - return unknown data.
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