LAN83C175 Datasheet, PDF (13/92 Pages) SMSC Corporation – Ethernet CARDBUS Integrated Controller With Modem Support

always contain the number of bytes to be
transmitted on the network, and not necessarily
the number of bytes in the transmit buffers. The
transmit DMA will begin copying data from the
location in host memory specified by the Buffer
Address field in the first descriptor. It will
compare the transmit byte count to the Data
Length field, and copy the lesser number of
bytes into the local transmit RAM. If early
transmit is enabled, the LAN83C175 will
automatically initiate transmission on the
network when the number of bytes specified in
the Early Transmit Threshold register have been
loaded into the transmit buffer.
If the transmit byte count is less than the Data
Length field, or the LASTDESCR bit is set, then
the frame copy is complete after the buffer has
been read. The LAN83C175 will initiate
transmission on the network if it has not already
done so.
If the Data Length field is less than the transmit
byte count and the LASTDESCR bit is not set,
then the LAN83C175 will attempt to read
another descriptor. The transmit DMA will
proceed as before, however this time it will not
read the Transmit Length field, but instead use
the remaining number of bytes in its transmit
byte counter (original byte count minus bytes
already copied). This process will continue until
a descriptor is read with the LASTDESCR bit set
or the transmit byte count reaches zero. If
LASTDESCR is set and the total number of
bytes copied do not add up to the transmit byte
count, then the transmit MTU will pad the frame
with random data after copying all of the valid
data out of the transmit RAM. The CSMA/CD
state machine will not append the automatically
generated CRC to the frame if NOCRC is set in
the last descriptor for the frame.
After the LAN83C175 has initiated the first
transmission, it will check to see if there are any
more frames in the transmit queue. If the
software does not have another frame ready for
transmission, then the ownership bit in the next
descriptor must be 0. If the ownership bit is 0,
then the LAN83C175 will clear TXQUEUED and
set the transmit queue empty interrupt. If the
ownership bit is 1, then the LAN83C175 will
begin copying the next frame into the local
transmit RAM. The DMA will continue copying
transmit buffers until the frame has been
completely loaded into the transmit RAM or the
first transmission has completed. If the copy
completes while the first transmission is still in
progress, then the LAN83C175 will stop and
wait. When the transmission is finished, the
LAN83C175 will post the status into the first
descriptor for that frame and immediately
initiate the second transmission. If the
transmission completes before the copy is done,
the LAN83C175 will pause after the current
transmit buffer has been copied and post the
status from the first frame. If the early transmit
threshold has already been exceeded then the
second transmission will be
initiated
immediately. The transmit DMA will then
continue by reading the next descriptor for the
copy in progress.
When the transmit status is posted, the
ownership bit will be written as 0 to indicate that
the host now owns that descriptor again. The
Transmit Length field will not be overwritten. If
TXIAF is true in the last descriptor for the frame,
then the transmit complete (TXC) interrupt will
be set. When there are no frames left in the
queue and the last transmission has completed
on the network, the transmit DMA will set the
transmit chain complete (TCC) interrupt and
return to its idle state.
2) Fragment List Method (descriptor points
to a fragment list)
This method of queuing a transmit frame is
much like the first method, except that each
frame is always specified by one descriptor
which points to a list of buffers (fragment list)
instead of the buffers themselves. The
FRAGLIST bit in the descriptor must be set to 1
and the LFFORM bit must properly indicate the
format of the fragment list. The first entry in the
fragment list tells how many data buffers
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