LAN83C175 Datasheet, PDF (56/92 Pages) SMSC Corporation – Ethernet CARDBUS Integrated Controller With Modem Support

10 through 2: THRESHOLD
1 and 0: Not writable - return unknown data.
Note: There are a set of configuration
registers for both the Ethernet and modem
function.
E0 - CardBus EARLY TRANSMIT COUNT
Reset Value: xxxxxxxxx
This counter contains the number of bytes to
be copied into the local transmit buffer before
the early transmit threshold is reached. The
counter is loaded with the early transmit
threshold value at the beginning of each frame
and counts down to zero. This register is
automatically written with the same data as
the ETXTHR register whenever a write to that
register occurs.
31 through 11 - Unused.
10 through 2 - Early Transmit Count.
1 and 0 - Not writable - return unknown data.
E4 - CardBus TRANSMIT DMA STATUS
Reset Value: xxxxxxxxxxxxx
This register contains a copy of the transmit
status from the most recently completed
transmission. The value is stored in this
register until it can be posted to the transmit
descriptor chain. Data from the host may not
be written into this register. When the register
is written by the host, it will be loaded with the
current value in the TXSTAT register. Reads
work normally.
The transmit length register and transmit length
counter are also writable through the upper word
at this address.
31 through 16 - TRANSMIT LENGTH: When this
register is written, these bits are stored into both
the transmit length register and transmit length
counter. These bits are not readable, and return
unknown data when read.
15 - OWNER: Descriptor ownership bit - This bit
is writable at this location but may only be read at
bit 21 in the PTDLGTH register. When read here,
this bit always returns 0 to set descriptor
ownership to the host.
14 through 13 - Unused.
12 through 8 - COLLISION COUNT: These bits
contain the number of collisions detected while
attempting to transmit the current packet. Bit 12
also indicates transmit abort for excessive
collisions.
7 - DEFERRING: This bit is set when the
interframe gap state machine is deferring. If the
PHY has asserted the collision line as a result of
jabber, this bit will stay set indicating the jabber
condition. Always returns 0.
6 - OUT OF WINDOW COLLISION: This bit is
set if a collision is detected more than one slot
time after the start of transmission. Transmission
is aborted under these conditions.
5 - COLLISION DETECT HEARTBEAT: This bit
is set to a ‘1’ during transmission of each packet.
It is set to ‘0’ if a collision is detected within 36 bit
times of the end of each packet transmission. If
no collision is detected within this window, it
remains ‘1’. This bit always returns zero in full
duplex mode.
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