LAN83C175 Datasheet, PDF (34/92 Pages) SMSC Corporation – Ethernet CARDBUS Integrated Controller With Modem Support

The remaining words in the EEPROM are
available to software for general purpose non-
volatile storage. The eeprom can be accessed
through the base address designated by the
Expansion Rom Base Address in the
configuration space for both the modem and
ethernet function.
POWER DOWN MODE
The LAN83C175 has a power down feature
which allows it to consume less power when not
in use. The host may power down the
LAN83C175 by writing a 1 to the power down bit
in the general control register. When the bit is
set, the chip's internal system clock is gated off
to reduce switching current (the transmit and
receive clocks will be shut off internally if the
LAN83C175 is in loopback mode when power
down is set). While the LAN83C175 is powered
down, the host may read and write the
configuration registers or the general control
register. All other functions are disabled
(attempting any other operation will cause
unpredictable behavior). The power down bit
must only be set when the LAN83C175 is in its
idle state.
When the nRST pin is asserted, the LAN83C175
will automatically enter power down mode after
recalling the contents of the EEPROM. The
host may power up the LAN83C175 by writing a
0 to the power down bit. If the host wishes to
issue a software reset to the LAN83C175, the
power down bit must be cleared. When the
software reset has completed, the power down
bit will remain cleared and the LAN83C175 will
be ready to operate.
The power down bit does not affect the CardBus
clock inside the LAN83C175. Instead, the
LAN83C175 supports the CardBus clock run
function which allows the host system to slow
down or temporarily shut off the CardBus clock
at its source. The clock run function is
implemented according to the CardBus Mobile
design guide (revision 1.0).
JUMPER OPTIONS
There are several operational modes in the
LAN83C175 which are selected by "jumpers" at
power-up reset. Actual jumpers do not need to
be installed on the board. The options can be
set by external pull-up or pull-down resistors at
manufacturing time. Pins MD[2:0] are used to
make the jumper selections. The pins are
latched shortly after nRST goes inactive. The
jumpers are not sampled after soft reset. A pull-
down resistor sets the jumper value to 0, and a
pull-up sets it to 1. The jumpers are defined as
follows:
MD[2] BYPASS EEPROM RECALL - When set
to 1, the EEPROM recall is not performed after
power-up reset. Used for test purposes only.
MD[1:0] These should be pulled down to 0.
SOFT RESET
The software driver may reset the LAN83C175
to its initial state by setting the soft reset bit in
the general control register. All state machines
and pointers to the internal RAMS will be reset.
Soft reset can only take place when the
LAN83C175 is powered up. Soft reset does
NOT affect the configuration of the LAN83C175.
The configuration registers (excluding EEPROM
control) will only be reset and the EEPROM will
only be recalled after hard reset.
Each time the software driver is loaded, it must
set soft reset before enabling the LAN83C175 to
act as a bus master. The driver may be loaded
after a warm boot, and the LAN83C175 DMA
controllers could be left in an unknown state.
If the LAN83C175 is enabled as a bus master
before a soft reset is issued, the DMA
controllers could corrupt host memory with a
bus master operation that was started before the
warm boot. When the soft reset bit is set, the
LAN83C175 takes 15 CardBus clocks to re-
initialize itself. The device must not be
accessed within that time period.
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