LAN83C175 Datasheet, PDF (24/92 Pages) SMSC Corporation – Ethernet CARDBUS Integrated Controller With Modem Support

Stopping the Receive DMA
The receive DMA may be halted by setting the
STOP_RDMA bit in the command register.
Setting this bit forces RXQUEUED to 0. The
CSMA/CD receiver should also be taken off-line
to prevent it from continuing to buffer receive
frames. The receive DMA will attempt to
complete any copy in progress. When finished,
it will return to its idle state. When the
CSMA/CD receiver is off-line and has also
returned to its idle state, the RXIDLE bit in the
interrupt status register will become true (1). If
the DMA reads a descriptor owned by the host
before it completes its current copy, it will set
the receive queued empty interrupt and return to
the idle state. The DMA will continue the copy
when more buffers are queued. The software
driver can tell if a copy is still in progress or
if there are any more frames in the local receive
RAM by reading the RCIP and RBE bits in the
interrupt status register.
The STOP_RDMA bit can be set when the
receive DMA has read and saved the
information in a descriptor, but there are no
frames in the local receive RAM. In this case,
the receive DMA will reset its current descriptor
pointer back to that descriptor and return to the
idle state. When the RXQUEUED bit is set
again, the DMA will be re-read the descriptor.
Maximum Receive Size and Burst Rate:
The receive DMA supports frame sizes up to 64
Kbytes. The maximum size for a single data
buffer (fragment) is also 64 Kbytes. The receive
DMA will run at the maximum CardBus data
rate of 132 Mbps when the target memory
system supports zero wait state writes. DMA
bursts at this rate will run for a limited number
of dwords. The length of each burst is
dependent on the FIFO threshold level and
access to the local receive RAM. The receive
DMA loads data into the receive burst FIFO at a
maximum rate of 100 Mbps (when reception is
not in progress) or 83 Mbps (when reception is
in progress).
The receive DMA will
automatically initiate a burst on the CardBus
bus whenever the FIFO reaches programmed
threshold level. The receive DMA will continue
to load data into the FIFO while it is being
emptied onto the CardBus bus. The burst will
continue until the FIFO is empty or the receive
DMA loses control of the CardBus bus (to the
internal transmit DMA or to another CardBus
master). Another burst will begin when the
FIFO again reaches the threshold level, or when
the last of the data for the current copy has been
loaded into the FIFO. The CardBus bus will be
requested immediately if the receive DMA loses
possession of the bus while the FIFO is above
the threshold level.
THR_SEL
[1]
0
0
1
1
THR_SEL
[0]
0
1
0
1
THRESHOLD
LEVEL
1/4 Full (32
Bytes)
1/2 Full (64
Bytes)
3/4 Full (96
Bytes)
Full (128 Bytes)
24