LAN83C175 Datasheet, PDF (61/92 Pages) SMSC Corporation – Ethernet CARDBUS Integrated Controller With Modem Support

performs bus master transactions to two
different devices (always returns 0).
8 - nSERR ENABLE: When this bit is set the
LAN83C175 may assert nSERR. When this
bit is cleared nSERR signalling is disabled.
7 - WAIT CYCLE CONTROL: This bit is not
implemented because the LAN83C175 does
not do address/data stepping (always returns
0).
08 - CLASS CODE / REVISION ID
31 through 24 - BASE CLASS: This read only
field returns the Network Controller Base Class
(02h). This returns (07h) when reading from the
modem configuration space.
23 through 16 - SUB CLASS: This read only field
returns the Ethernet Controller Sub-Class (00h).
Also returns (00h) reading from the modem
configuration space.
6 - PARITY ERROR RESPONSE: When this
bit is set the LAN83C175 will respond to parity
errors. When cleared, the LAN83C175 will
ignore parity errors.
5 through 3 - VGA PALETTE SNOOP,
MEMORY WRITE AND INVALIDATE
ENABLE, SPECIAL
CYCLES:
Not
implemented (always return 0).
2 - BUS MASTER ENABLE: The LAN83C175
may only act as bus master on the CardBus
bus when this bit is set. When this bit is
cleared the LAN83C175 will disable its
CardBus request signal.
1 - MEMORY SPACE ENABLE: The
LAN83C175 may respond to memory space
accesses when this bit is set. When the bit is
cleared, the LAN83C175 will not respond to
memory space accesses.
0 - I/O SPACE ENABLE: The LAN83C175
may respond to I/O space accesses when this
bit is set. When the bit is cleared, the
LAN83C175 will not respond to I/O space
accesses.
15 through 8 - PROGRAMMING INTERFACE:
This read only field returns 00h (no specific
register-level programming interface defined).
This returns (02h) is read from the modem
configuration space.
7 through 0 - REVISION ID: This read only field
returns the LAN83C175 silicon revision ID (00h
for XA). This returns (00h) in both configuration
spaces.
0C - HEADER TYPE / LATENCY TIMER
31 THROUGH 24: Unused (returns 00h).
23 - MULTI-FUNCTION DEVICE: This bit returns
1 to indicate that the LAN83C175 is a multi
function CardBus device.
22 through 16 - HEADER TYPE: Specifies the
format of bytes 10h - 3Ch in the configuration
space (00h).
15 through 8 - LATENCY TIMER: This byte is
programmed with the value of the Latency Timer
(in CardBus bus clocks) for LAN83C175 bus
master operations. The bottom three bits are
hardwired to 0, giving the latency timer a
granularity of 8 clocks. This register is 00h after
reset.
7 through 0: Unused (returns 00h).
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