LAN83C175 Datasheet, PDF (41/92 Pages) SMSC Corporation – Ethernet CARDBUS Integrated Controller With Modem Support

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7 - TRANSMIT DMA PRIORITY: When this bit
is set, the transmit DMA may preempt the
receive DMA for access to the CardBus bus.
Preemption occurs when the CardBus latency
timer expires.
6 - RECEIVE DMA PRIORITY: When this bit
is set, the receive DMA may preempt the
transmit DMA for access to the CardBus bus.
Preemption occurs when the CardBus latency
timer expires.
5 - BIG ENDIAN: This bit controls the order of
the bytes on the data bus when the
LAN83C175 is used in a big endian machine.
When this bit is set to 1, the LAN83C175
performs byte swapping on the descriptor and
fragment list entries to compensate for byte
swapping by the CardBus bridge.
4 - ONECOPY: When this bit is set to 1, the
LAN83C175 will give the host only one copy
of each receive frame. This bit causes
NEXTFRAME to be set automatically at the
end of each frame. This bit should not be
modified while the receive DMA is not idle.
3 - POWER DOWN: Setting this bit puts the
LAN83C175 into a low power sleep mode.
When this bit is cleared (I/O writes to this
register are still enabled in sleep mode) the
LAN83C175 will resume in the state it was in
prior to power down. This bit may only be set
when the chip is idle.
2 - SOFTWARE INTERRUPT: When this bit is set
to a 1, the LAN83C175 interrupt pin nINTA will
become active (driven low).
1 - INTERRUPT ENABLE: Setting this bit enables
the LAN83C175 interrupt line. When one of the
interrupt status bits and its corresponding mask
bit are both set, the LAN83C175 will drive the
nINTA pin low. Clearing this bit masks all
interrupts (except software interrupt).
0 - SOFT RESET: Setting this bit to a 1 resets the
LAN83C175 to its initialization state. All state
machines and pointers to the internal rams will
be reset. The configuration registers (except
EEPROM control) and non-volatile control register
will NOT be reset and EEPROM recall will not
take place after a soft reset. This register will
return to its reset value after the operation is
complete, regardless of the data written.
10 - NON-VOLATILE CONTROL
Power Up Reset Value: 000000
31 through 15: Unused
14 - FETPWRPHY: This bit controls the
FETPWRPHY output signal that is used to control
a powerdown signal to the physical layer. Upon
reset, it will be zero, and will then reflect the value
loaded into it during EEPROM recall.
13 - MULTI_FUNC: This bit is read during
configuration on bit 23 when the hdr type and
latency timer are read.
12 - STSCHG_EN: This bit must be high to allow
the function event register for the modem to be
driven out onto the cardbus.
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