LAN83C175 Datasheet, PDF (32/92 Pages) SMSC Corporation – Ethernet CARDBUS Integrated Controller With Modem Support

Timers and Counters/Slot Timer
During transmit, the slot timer starts counting
once the receiver recognizes that a carrier is
present at the start of a returning preamble.
When backing off, the slot timer starts with the
end of transmit enable (TX_EN) for the collided
frame and is not reset by any other incoming
frames. The slot timer is programmable by the
transmit control register. The default slot time is
512 bit times.
Backoff Timer
After a transmission is terminated because of a
collision, a retransmission is attempted. The
backoff time is determined by the truncated
binary exponential backoff alogrithm. This
algorithm is:
draw random integer r: 0<=r<2**k
Where k equals the number of retries already on
this transmission. The value k is initialized to 0.
The required backoff time is 'r' number of slot
times. After the backoff time has been
completed, normal transmission deferral begins.
The backoff timer is a 12 bit counter that is
initialized to a random number when an
attempted transmission results in a collision.
The counter decrements once per slot time until
it reaches zero. The transmit protocol FSM
utilizes this timer to insert a variable amount of
delay ahead of its attempt to retransmit the
frame.
Collision Counter
Prior to the first attempt at each frame
transmission, the collision counter is initialized
to 0. Each attempted transmission of the frame
resulting in a collision causes the collision
counter
to increment. If the maximum number of
collisions (16) is reached before a successful
attempt to transmit the frame, the frame
transmission is aborted. An interrupt is
generated for an aborted frame indicating
transmission complete, and the collision count
value in the transmit status register is 16.
Heartbeat Detection
When the transmitter is configured in serial
mode, after each transmission, the transmit
logic opens a window 3.6 µsec long during
which it looks for a pulse on the COL pin. This
pulse is normally generated by the MAU and is
received through the MII interface. If the pulse
is received, the CDH status bit of the transmit
status register is cleared. If no pulse is received,
the CDH bit is set.
MII MANAGEMENT INTERFACE
The LAN83C175 supports the 802.3
specification for the MII Serial Management
Interface.
EEPROM INTERFACE
The LAN83C175 has a 8-bit parallel interface to
an external EEPROM. The parallel EEPROM
contains the LAN Address for the adapter and a
several bytes of configuration information. The
LAN address and configuration information is
automatically recalled from the first eight words
(each word is 16 bits) of the serial EEPROM
after reset. Access to the LAN83C175 is
disabled during the initial EEPROM recall. Any
attempted access results in a CardBus target
retry. The initial recall may be bypassed
through a test "jumper".
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