LAN83C175 Datasheet, PDF (38/92 Pages) SMSC Corporation – Ethernet CARDBUS Integrated Controller With Modem Support

REGISTER DESCRIPTIONS/CONTROL
REGISTERS
00 - COMMAND
Reset Value: 0000000
31 through 8 - Reserved: These bits will return
unknown values and should never be written
to 1.
7 - TXUGO: This bit is set to restart
transmission after a transmit underrun error.
Setting this bit automatically clears the
transmit underrun interrupt. Writing a zero to
this bit has no effect. This bit always returns 0
when read.
6 - STOP_RDMA: This bit is used to halt the
receive DMA. Writing a 1 to this bit clears
RXQUEUED. Writing a 0 to this bit has no
effect. This bit always returns 0 when
read.
5 - STOP_TDMA: This bit is used to halt the
transmit DMA. Writing a 1 to this bit clears
TXQUEUED. Writing a 0 to this bit has no
effect. This bit always returns 0 when read.
4 - NEXTFRAME: This bit is set by the host to
indicate that it does not need any more copies
of the current receive frame. The bit will be
cleared by the LAN83C175 the next time it
reads a descriptor. Writing a 0 to this bit has
no effect (in register test mode writing 0
clears the bit).
3 - RXQUEUED: This bit is set to queue a
receive descriptor. It will be cleared by the
LAN83C175 when it reads a descriptor that is
still owned by the host. Setting this bit
automatically clears the receive queue empty
interrupt. Writing a 0 to this bit has no effect
(in register test mode writing 0 clears the bit).
The host may clear this bit by writing a 1 to
RDMA_STOP.
2 - TXQUEUED: This bit is set to queue a
transmit descriptor. It will be cleared by the
LAN83C175 when it reads a descriptor that is still
owned by the host. Setting this bit automatically
clears the transmit queue empty interrupt.
Writing a 0 to this bit has no effect (in register test
mode writing 0 clears the bit). The host may clear
this bit by writing a 1 to TDMA_STOP.
1 - START_RX: Writing a 1 to this bit will bring
the LAN83C175 receiver online. When this bit is
cleared the receiver will stay online until the stop
bit is set.
0 - STOP_RX: Writing a 1 to this bit will take the
LAN83C175 receiver off-line. When this bit is
cleared the receiver will stay off-line until the start
bit is set.
04 - INTERRUPT STATUS
Reset Value: 01001100000000000000000
Bits in this register are set internally by the
LAN83C175. Bits are cleared by writing a 1 to
their respective locations. Writing 0 to a bit has
no effect (in register test mode writing 0 sets the
bit).
31 through 28 - Unused
27 - PTA: CardBus Target abort - set when
EPIC/C cannot complete a bus master transaction
because target aborts the transaction.
26 - PMA: CardBus Master abort - set when
EPIC/C cannot complete a bus master transaction
because no target is found.
25 - APE: CardBus address parity error - set
when an address parity error occurs on the
CardBus bus while EPIC/C is not bus master.
This interrupt will only be set when the Parity
Error Response bit in the CardBus configuration
space is set.
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