LAN83C175 Datasheet, PDF (12/92 Pages) SMSC Corporation – Ethernet CARDBUS Integrated Controller With Modem Support

DWORD 1 - Data Buffer/Start of Fraglist Pointer
Bit Number and Description
31 through 0: Starting address of data buffer or
fragment list in host memory space. Fragment
list must be DWORD aligned. Data buffer may
be aligned on any byte.
DWORD 2 - Control/Data Length
Bit Number and Description
31 through 21 Reserved: Must always be set to
0.
20 - LASTDESCR: Indicates that this is the last
descriptor for the current transmit frame (Not
used when FRAGLIST = 1).
19 - NOCRC: Disable automatic CRC
generation for this packet when set.
18 - IAF: When set, interrupt after this frame is
transmitted.
17 - LFFORM: Fragment list format - A "1"
indicates that the data length field comes before
the pointer in the fragment list. "0" indicates
that the pointer comes before the data length.
16 - FRAGLIST: Indicates that this descriptor
points to a fragment list.
15 through 0 - Length of data buffer (Not used
when FRAGLIST = 1).
DWORD 3 - Next Descriptor Pointer
Bit Number and Description
31 through 2 - Starting address of next
descriptor in host memory space. Descriptors
must be DWORD aligned.
1 - 0: Unused.
The software driver initializes the transmit
process by writing the transmit control register,
early transmit threshold register (if early
transmit will be used), inter-packet gap program
register, interrupt mask register and general
control register. The software must also
program the CardBus Transmit Current
Descriptor Address Register (PTCDAR) with the
address in host memory where the first transmit
descriptor will be located.
To begin packet transmissions, the software
driver programs the transmit descriptor chain
with the appropriate number of entries and then
sets the TXQUEUED bit in the COMMAND
register.
Descriptor entries describe the location of
transmit data in host memory. Data for a single
transmit frame may not always be in a
contiguous block in host memory. Therefore,
the LAN83C175 allows the software to specify
multiple data buffers for each frame. Each
frame may be queued in one of two ways, both
of which may be used in the same descriptor
chain:
1) Direct Queuing Method (descriptors point
directly to the transmit data buffers):
One or more descriptors may be used to point
to a single frame. All descriptors must have the
FRAGLIST control bit set to 0. The first
descriptor must contain the transmit length for
the frame. The last descriptor for the frame
must have the LASTDESCR bit set to 1 and
contain the desired values for the TXIAF and
NOCRC control bits. When the TXQUEUED bit
is set, the transmit DMA will read the from the
location in host memory pointed to by its
Current Descriptor Address register. If the
ownership bit in the descriptor is equal to 1 then
the LAN83C175 will accept the descriptor and
update its Current Descriptor Address register
with the value in the Next Descriptor Address
field. Otherwise the TXQUEUED bit will be
cleared (and the transmit queue empty (TQE)
interrupt set) and the Current Descriptor
Address register will not be changed. The
Transmit Length field in the first descriptor will
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