LAN83C175 Datasheet, PDF (25/92 Pages) SMSC Corporation – Ethernet CARDBUS Integrated Controller With Modem Support

A lower threshold allows the LAN83C175 to
begin moving data on the CardBus bus sooner,
while a higher threshold may allow longer
bursts. A higher threshold level will not result in
parity generation and error detection. This block
is also responsible for responding to all slave
operations according to CardBus bus protocol
(including address recognition and parity
generation and error detection).
TRANSMIT/RECEIVE ARBITRATION FOR
CardBus BUS
Another major function of the CardBus Bus
Master/Slave Interface block is to arbitrate
between the transmit and receive DMA
controllers for access to the CardBus bus. Two
programmable priority select bits determine the
relative priority of each DMA controller. When
RXPRI is set, the receive DMA process may
preempt the transmit DMA process (when the
CardBus Latency Timer expires). The receive
DMA takes control of the CardBus bus if a
transmit fragment copy is suspended by a
target disconnect before the Latency Timer
expires. When RXPRI is cleared, the receive
process has to wait until the transmit DMA is
finished before it has access to the CardBus
bus. When TXPRI is set, the transmit DMA
process may preempt the receive DMA process
(when the CardBus Latency Timer expires). The
transmit DMA also takes control of the CardBus
bus if a receive fragment copy is suspended
by a target disconnect before the Latency
Timer expires. When TXPRI is cleared, the
transmit process has to wait until the receive
DMA is finished before it has access to the
CardBus bus. When both bits are set, either
process may preempt the other. When neither
bit is set, no preemptions occur. (Note:
Preemption does not occur when either process
has only one dword left to transfer).
SYSTEM ERRORS
There are four types of CardBus bus errors that
are considered fatal by the LAN83C175. They
are Master Abort, Target Abort, Address Parity
Error and Data Parity Error (see interrupt status
register for details). If any of these errors
occurs, the LAN83C175 will set the appropriate
interrupt and immediately discontinue all DMA
activity. The receiver will automatically be taken
off-line and any transmissions in progress will
be completed without a valid CRC appended (in
case transmit data was corrupted). Normal
operation may only be resumed by resetting the
LAN83C175 with the soft reset bit. The
software driver should make sure the transmitter
and receiver have returned to their idle states
(by polling the TXIDLE and RXIDLE bits in the
interrupt status register) before resetting the
device.
BIG/LITTLE ENDIAN SUPPORT
In order to run in Big Endian machines, the
LAN83C175 can be programmed to swap bytes
on the data bus in certain circumstances. In
Macintosh Power PC computers the bridge
between the Big Endian processor data bus and
the Little Endian CardBus bus swaps the order
of the bytes on the data bus (during data phase
only - addresses are never modified). This
means that byte size quantities transferred over
the data bus will always end up in the correct
location for their given address, but when 32 bit
(dword) quantities are transferred they will end
up with their bytes reversed.
When programmed into Big Endian mode,
the LAN83C175 will automatically swap the data
bytes internally when reading or writing
descriptor tables or fragment lists. This allows
the software driver to treat the descriptor and
fragment list entries as 32 bit quantities and not
worry about byte ordering.
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