LAN83C175 Datasheet, PDF (29/92 Pages) SMSC Corporation – Ethernet CARDBUS Integrated Controller With Modem Support

Computation stops after the reception of the last
whole byte following loss of carrier in serial
mode or the transition of RX_DV from active to
inactive in parallel mode. The final value of the
CRC must be "C704DD7B" for the packet to be
validated. The CRC polynomial used is
AUTODIN II (X32 + X26 + X23 +X22 + X16 +
X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 +
X1 + 1).
In addition, in parallel mode, the receive error
signal, RXER, forces a CRC error when it is
asserted while RX_DV is active.
Address Recognition
The receiver is capable of recognizing
individual, multicast, and broadcast addresses.
It can also be programmed to operate in
promiscuous mode and receive all frames
regardless of address. In all cases, address
recognition begins with the first byte following
SFD and ends with the sixth byte after SFD.
Individual destination addresses are compared
against a 6 byte register station address.
Multicast addresses are recognized by taking a
6 bit snapshot of the partially computed CRC
as the end of the destination address field
passes through the CRC checker. If the address
has the multicast bit set, the 6 bits are used
as a hashed index to a 64 bit Multicast Filter
table. If reception of multicast frames has been
enabled and if the 6 bit hash index points to a bit
in the table that has been set, the multicast
frame will be recognized. Broadcast frames are
received when the broadcast enable bit is set
and the destination address specifies a
broadcast frame, or when the hashed bit in the
Multicast Filter table has been set.
Reception of all multicast and broadcast frames
can be achieved by setting all bits in the
Multicast filter table and enabling reception of
multicast frames. If the address is not
recognized by any of the above means, then the
frame will be ignored.
When an address is recognized, the entire
frame will be saved into local memory.
Frame Processing
Frame processing begins following the detection
of SFD and continues until the last bit or nibble
of the frame has been received. Frame
processing counts the number of bytes in the
receive frame, transfers data to the receive
FIFO, checks for errors in both size and data,
posts status, generates interrupts, and counts
events. Frame processing can be controlled by
the receive control register to allow flexible
control of frame reception.
Receive Byte Count
The receive byte counter begins counting with
the first byte of SFD and counts all bytes of the
frame until the end of frame is detected or an
error condition causes the frame processing to
be aborted. The counter filters runt frames by
comparing the current byte count value to the
slot time programmed in the Transmit Control
register. The frame is considered a runt until
the byte count exceeds the slot time value. Runt
frames are not received under default
conditions. Reception of runt frames can be
enabled by setting the receive runts bit in the
receive control register.
Data Transfer
Receive data is stored temporarily in a 8-dword
receive FIFO. Data begins to be stored in the
FIFO after detection of SFD. If the destination
address is not recognized, data stops being
transferred into the FIFO and the FIFO is reset.
When the FIFO level reaches 6-dwords, a burst
request to the local receive memory is made.
The return of acknowledge is guaranteed to
prevent the receive FIFO from overflowing. The
data path to the receive local memory is 32-bits.
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