LAN83C175 Datasheet, PDF (28/92 Pages) SMSC Corporation – Ethernet CARDBUS Integrated Controller With Modem Support

MAC Operation
The LAN83C175 is compliant with the 802.3
standard CSMA/CD protocol for 10 or 100
Mbps Ethernet networks.
MAC Receiver
The LAN83C175 CSMA/CD receiver is capable
of operating with network data rates of 10 and
100 Mbps. It supports current implementations
of 10 Mbps physical layer devices, and the
802.3u Media Independent Interface for 10 and
100 Mbps.
Basic Function
The receiver processes serial or nibble wide
data streams at data rates of 10 Mbps or 100
Mbps. The receiver detects start of frame,
provides destination address recognition and
filtering, transfers recognized frames to
memory, and provides error detection and
reporting.
Interface to Physical Layers
The receiver interfaces to the physical layer in
serial or parallel mode. When in the serial
mode, data is transferred serially on the RXD[0]
pin synchronous to the falling edge of the
receive data clock (RX_CLK). RX_CLK is a 10
MHz clock signal recovered by the physical layer
device from the data stream. The CRS and
COL signals provide carrier sense and collision
detect respectively.
In parallel mode, the physical layer device
transfers data to the LAN83C175 four bits at a
time on the RXD[3-0] data bus. The data is
transferred synchronously to the falling edge of
RXC. The signal Receive Data Valid (RX_DV)
informs the MAC of the RXD bus status. The
physical layer can also notify the LAN83C175 of
invalid data on the medium with the Receive
Error signal (RX_ER). Selecting the receiver
interface mode is performed by programming
the MII Configuration register.
Packet Reception/Serial Mode
After detection of carrier, serial bits received on
RXD[0] are synchronized to the rising edge of
RX_CLK. Each bit is shifted through an 8-bit
shift register scanning for a Start of Frame
Delimiter (SFD) pattern of '10101011' received
from left to right. Following detection of SFD, all
bits are byte aligned in the serial to parallel shift
register. Bits are received from least significant
bit to most significant bit within the byte. Data
from the shift register is transferred to the
receive FIFO where it waits for the receive DMA
to transfer it into local memory. The receive
process continues while CRS or COL are active.
Parallel Mode
Packet reception begins with the first nibble after
detecting RX_DV active. Nibbles transferred on
RXD[3-0] are synchronized to the rising edge
of RX_CLK and shifted into a 2-nibble shift
register. RXD[0] is the least significant bit
(LSB). SFD is detected when the shift register
contains the value '10101011' from LSB to
MSB. The preamble and SFD pattern received
from the PHY device is required to be nibble
aligned. Bytes are aligned in the 2-nibble shift
register after detection of SFD. Each byte is
transferred to the receive FIFO. Packet
reception continues while RXDV is active and
ends with the nibble preceding the falling edge
of RX_DV. While RX_DV is de-asserted, the
value of RXD[3-0] has no effect on the MAC.
Error Detection
The receiver computes the CRC of incoming
frames for all data following the detection of
SFD in both parallel and serial mode until the
end of frame, including the CRC field.
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