C8051F330-GMR Datasheet, PDF (95/210 Pages) Silicon Laboratories – Mixed-Signal ISP Flash MCU

C8051F330/1/2/3/4/5
10.1. Power-On Reset
During power-up, the device is held in a reset state and the RST pin is driven low until V_DD settles above
V_RST. A delay occurs before the device is released from reset; the delay decreases as the V_DD ramp time
increases (V_DD ramp time is defined as how fast V_DD ramps from 0 V to V_RST). Figure 10.2. plots the
power-on and V_DD monitor reset timing. The maximum V_DD ramp time is 1 ms; slower ramp times may
cause the device to be released from reset before V_DD reaches the V_RST level. For ramp times less than
1 ms, the power-on reset delay (T_PORDelay) is typically less than 0.3 ms.
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. When PORSF is
set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is cleared by all other
resets). Since all resets cause program execution to begin at the same location (0x0000) software can
read the PORSF flag to determine if a power-up was the cause of reset. The content of internal data mem-
ory should be assumed to be undefined after a power-on reset. The V_DD monitor is disabled following a
power-on reset.
VDD
2.70
2.55
V_RST
2.0
1.0
t
/RST
Logic HIGH
Logic LOW
T_PORDelay
Power-On
Reset
VDD
Monitor
Reset
Figure 10.2. Power-On and V_DD Monitor Reset Timing
10.2. Power-Fail Reset/V_DD Monitor
When a power-down transition or power irregularity causes V_DD to drop below V_RST, the power supply
monitor will drive the RST pin low and hold the CIP-51 in a reset state (see Figure 10.2). When V_DD returns
to a level above V_RST, the CIP-51 will be released from the reset state. Note that even though internal data
memory contents are not altered by the power-fail reset, it is impossible to determine if V_DD dropped below
the level required for data retention. If the PORSF flag reads ‘1’, the data may no longer be valid. The V_DD
monitor is disabled after power-on resets; however its defined state (enabled/disabled) is not altered by
any other reset source. For example, if the V_DD monitor is enabled and a software reset is performed, the
V_DD monitor will still be enabled after the reset.
98
Rev. 1.7