C8051F330-GMR Datasheet, PDF (109/210 Pages) Silicon Laboratories – Mixed-Signal ISP Flash MCU

C8051F330/1/2/3/4/5
13. Oscillators
C8051F330/1/2/3/4/5 devices include a programmable internal high-frequency oscillator, a programmable
internal low-frequency oscillator, and an external oscillator drive circuit. The internal high-frequency oscilla-
tor can be enabled/disabled and calibrated using the OSCICN and OSCICL registers, as shown in
Figure 13.1. The internal low-frequency oscillator can be enabled/disabled and calibrated using the
OSCLCN register, as shown in SFR Definition 13.3. The system clock can be sourced by the external
oscillator circuit or either internal oscillator. Both internal oscillators offer a selectable post-scaling feature.
The internal oscillators’ electrical specifications are given in Table 13.1 on page 122.
OSCICL
OSCICN
OSCLCN
Option 3
XTAL2
Option 2
VDD
XTAL2
Option 4
XTAL2
Option 1
XTAL1
10M
XTAL2
EN
Programmable
Internal Clock
Generator
OSCLF
EN
Low Frequency
Oscillator
Input
Circuit
OSC
OSCLF OSCLD
n
n
OSCLD
SYSCLK
OSCXCN
CLKSEL
Figure 13.1. Oscillator Diagram
13.1. Programmable Internal High-Frequency (H-F) Oscillator
All C8051F330/1/2/3/4/5 devices include a programmable internal high-frequency oscillator that defaults
as the system clock after a system reset. The internal oscillator period can be adjusted via the OSCICL
register as defined by SFR Definition 13.1.
On C8051F330/1/2/3/4/5 devices, OSCICL is factory calibrated to obtain a 24.5 MHz base frequency.
Electrical specifications for the precision internal oscillator are given in Table 13.1 on page 122. Note that
the system clock may be derived from the programmed internal oscillator divided by 1, 2, 4, or 8, as
defined by the IFCN bits in register OSCICN. The divide value defaults to 8 following a reset.
Rev. 1.7
113