C8051F330-GMR Datasheet, PDF (94/210 Pages) Silicon Laboratories – Mixed-Signal ISP Flash MCU

C8051F330/1/2/3/4/5
10. Reset Sources
Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this
reset state, the following occur:
• CIP-51 halts program execution
• Special Function Registers (SFRs) are initialized to their defined reset values
• External Port pins are forced to a known state
• Interrupts and timers are disabled.
All SFRs are reset to the predefined values noted in the SFR detailed descriptions. The contents of internal
data memory are unaffected during a reset; any previously stored data is preserved. However, since the
stack pointer SFR is reset, the stack is effectively lost, even though the data on the stack is not altered.
The Port I/O latches are reset to 0xFF (all logic ones) in open-drain mode. Weak pullups are enabled dur-
ing and after the reset. For VDD Monitor and power-on resets, the RST pin is driven low until the device
exits the reset state.
On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to the inter-
nal oscillator. Refer to Section “13. Oscillators” on page 113 for information on selecting and configuring
the system clock source. The Watchdog Timer is enabled with the system clock divided by 12 as its clock
source (Section “19.3. Watchdog Timer Mode” on page 201 details the use of the Watchdog Timer).
Program execution begins at location 0x0000.
Px.x
Px.x
Comparator 0
+
-
C0RSEF
VDD
Supply
Monitor
+
-
Enable
Power On
Reset
'0'
(wired-OR)
/RST
Missing
Clock
Detector
(one-
shot)
EN
PCA
WDT
EN
System
Clock
CIP-51
Microcontroller ^{System Reset}
Core
Reset
Funnel
(Software Reset)
SWRSF
Errant
FLASH
Operation
Figure 10.1. Reset Sources
Rev. 1.7
97