C8051F330-GMR Datasheet, PDF (171/210 Pages) Silicon Laboratories – Mixed-Signal ISP Flash MCU

C8051F330/1/2/3/4/5
Table 17.1. SPI Slave Timing Parameters
Parameter
Description
Master Mode Timing^* (See Figure 17.8 and Figure 17.9)
T_MCKH
SCK High Time
T_MCKL
SCK Low Time
T_MIS
MISO Valid to SCK Shift Edge
T_MIH
SCK Shift Edge to MISO Change
Slave Mode Timing^* (See Figure 17.10 and Figure 17.11)
T_SE
NSS Falling to First SCK Edge
T_SD
Last SCK Edge to NSS Rising
T_SEZ
NSS Falling to MISO Valid
T_SDZ
NSS Rising to MISO High-Z
T_CKH
SCK High Time
T_CKL
SCK Low Time
T_SIS
MOSI Valid to SCK Sample Edge
T_SIH
SCK Sample Edge to MOSI Change
T_SOH
SCK Shift Edge to MISO Change
T_SLH
Last SCK Edge to MISO Change 
(CKPHA = 1 ONLY)
Min
Max
Units
1 x T_SYSCLK
—
ns
1 x T_SYSCLK
—
ns
1 x T_SYSCLK + 20
—
ns
0
—
ns
2 x T_SYSCLK
2 x T_SYSCLK
—
—
5 x T_SYSCLK
5 x T_SYSCLK
2 x T_SYSCLK
2 x T_SYSCLK
—
6 x T_SYSCLK
—
ns
—
ns
4 x T_SYSCLK ns
4 x T_SYSCLK ns
—
ns
—
ns
—
ns
—
ns
4 x T_SYSCLK ns
8 x T_SYSCLK ns
*Note: T_SYSCLK is equal to one period of the device system clock (SYSCLK).
Rev. 1.7
175