C8051F330-GMR Datasheet, PDF (129/210 Pages) Silicon Laboratories – Mixed-Signal ISP Flash MCU

C8051F330/1/2/3/4/5
SFR Definition 14.11. P2: Port2
R
R
R
R
R
R
R
R/W
Reset Value
-
-
-
-
-
-
-
P2.0 00000001
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 SFR Address:
(bit addressable)
0xA0
Bits7–1:
Bit0:
Unused. Read = 0000000b. Write = don’t care.
P2.0
Write - Output appears on I/O pins per Crossbar Registers.
0: Logic Low Output.
1: Logic High Output (high impedance if corresponding P2MDOUT.n bit = 0).
Read - Directly reads Port pin.
0: P2.n pin is logic low.
1: P2.n pin is logic high.
SFR Definition 14.12. P2MDOUT: Port2 Output Mode
R
R
R
R
R
R
R
R/W
Reset Value
-
-
-
-
-
-
-
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 SFR Address:
0xA6
Bits7–1:
Bit0:
Unused. Read = 0000000b. Write = don’t care.
Output Configuration Bit for P2.0.
0: P2.0 Output is open-drain.
1: P2.0 Output is push-pull.
Rev. 1.7
133