C8051F330-GMR Datasheet, PDF (33/210 Pages) Silicon Laboratories – Mixed-Signal ISP Flash MCU

C8051F330/1/2/3/4/5
4. Pinout and Package Definitions
Table 4.1. Pin Definitions for the C8051F330/1/2/3/4/5
Name
V_DD
GND
RST/
Pin
‘F330/1/2/
3/4/5-GM
Pin
’F330-GP
Type
Description
3
6
Power Supply Voltage.
2
5
Ground.
4
7
D I/O Device Reset. Open-drain output of internal POR or V_DD
monitor. An external source can initiate a system reset by
driving this pin low for at least 10 µs.
C2CK
P2.0/
5
D I/O Clock signal for the C2 Debug Interface.
8
D I/O Port 3.0. See Section 14 for a complete description.
C2D
P0.0/
1
D I/O Bi-directional data signal for the C2 Debug Interface.
4
D I/O or Port 0.0. See Section 14 for a complete description.
A In
VREF
P0.1
20
A In External VREF input. See Section 7 for a complete descrip-
tion.
3
D I/O or Port 0.1. See Section 14 for a complete description.
A In
IDA0
P0.2/
19
AOut IDA0 Output. See Section 6 for a complete description.
2
D I/O or Port 0.2. See Section 14 for a complete description.
A In
XTAL1
P0.3/
18
A In External Clock Input. This pin is the external oscillator
return for a crystal or resonator. See Section 13 for a com-
plete description.
1
D I/O or Port 0.3. See Section 14 for a complete description.
A In
XTAL2
P0.4
17
P0.5
16
A I/O or External Clock Output. For an external crystal or resonator,
D In this pin is the excitation driver. This pin is the external clock
input for CMOS, capacitor, or RC oscillator configurations.
See Section 13 for a complete description.
20 D I/O or Port 0.4. See Section 14 for a complete description.
A In
19 D I/O or Port 0.5. See Section 14 for a complete description.
A In
Rev. 1.7
35