C8051F330-GMR Datasheet, PDF (27/210 Pages) Silicon Laboratories – Mixed-Signal ISP Flash MCU

C8051F330/1/2/3/4/5
1.8. Comparators
C8051F330/1/2/3/4/5 devices include an on-chip voltage comparator that is enabled/disabled and config-
ured via user software. Port I/O pins may be configured as comparator inputs via a selection mux. Two
comparator outputs may be routed to a Port pin if desired: a latched output and/or an unlatched (asynchro-
nous) output. Comparator response time is programmable, allowing the user to select between high-speed
and low-power modes. Positive and negative hysteresis are also configurable.
Comparator interrupts may be generated on rising, falling, or both edges. When in IDLE mode, these inter-
rupts may be used as a “wake-up” source. Comparator0 may also be configured as a reset source.
Figure 1.15 shows the Comparator0 block diagram.
CMX0N3
CMX0N2
CMX0N1
CMX0N0
CMX0P3
CMX0P2
CMX0P1
CMX0P0
CP0EN
CP0OUT
CP0RIF
CP0FIF
CP0HYP1
CP0HYP0
CP0HYN1
CP0HYN0
VDD
P0.0
P0.2
P0.4
P0.6
P1.0
P1.2
P1.4
P1.6
P0.1
P0.3
P0.5
P0.7
P1.1
P1.3
P1.5
P1.7
CP0 +
CP0 -
+
-
GND
D ^SET Q
Q
CLR
D ^SET Q
Q
CLR
(SYNCHRONIZER)
Reset
Decision
Tree
CP0
Crossbar
CP0A
0
CP0RIF
1
0
CP0FIF
1
CP0EN
EA
0
1
CP0
0 Interrupt
1
CP0RIE
CP0FIE
CP0MD1
CP0MD0
Figure 1.15. Comparator0 Block Diagram
Rev. 1.7
29