C8051F330-GMR Datasheet, PDF (198/210 Pages) Silicon Laboratories – Mixed-Signal ISP Flash MCU

C8051F330/1/2/3/4/5
19.3.1. Watchdog Timer Operation
While the WDT is enabled:
• PCA counter is forced on.
• Writes to PCA0L and PCA0H are not allowed.
• PCA clock source bits (CPS2–CPS0) are frozen.
• PCA Idle control bit (CIDL) is frozen.
• Module 2 is forced into software timer mode.
• Writes to the Module 2 mode register (PCA0CPM2) are disabled.
While the WDT is enabled, writes to the CR bit will not change the PCA counter state; the counter will run
until the WDT is disabled. The PCA counter run control (CR) will read zero if the WDT is enabled but user
software has not enabled the PCA counter. If a match occurs between PCA0CPH2 and PCA0H while the
WDT is enabled, a reset will be generated. To prevent a WDT reset, the WDT may be updated with a write
of any value to PCA0CPH2. Upon a PCA0CPH2 write, PCA0H plus the offset held in PCA0CPL2 is loaded
into PCA0CPH2 (See Figure 19.10).
PCA0MD
CWW CCCE
I DD PPPC
DT L SSSF
LEC 210
K
PCA0CPH2
8-bit
Enable ^Comparator
Match
Reset
PCA0CPL2
Write to
PCA0CPH2
8-bit Adder
Adder
Enable
PCA0H
PCA0L Overflow
Figure 19.10. PCA Module 2 with Watchdog Timer Enabled
202
Rev. 1.7