C8051F330-GMR Datasheet, PDF (200/210 Pages) Silicon Laboratories – Mixed-Signal ISP Flash MCU

C8051F330/1/2/3/4/5
Table 19.4. Watchdog Timer Timeout Intervals¹
System Clock (Hz)
24,500,000
24,500,000
24,500,000
18,432,000
18,432,000
18,432,000
11,059,200
11,059,200
11,059,200
3,062,500²
3,062,500²
3,062,500²
32,000
32,000
32,000
PCA0CPL2
255
128
32
255
128
32
255
128
32
255
128
32
255
128
32
Timeout Interval (ms)
32.1
16.2
4.1
42.7
21.5
5.5
71.1
35.8
9.2
257
129.5
33.1
24576
12384
3168
Notes:
1. Assumes SYSCLK/12 as the PCA clock source, and a PCA0L value
of 0x00 at the update time.
2. Internal SYSCLK reset frequency = Internal Oscillator divided by 8.
19.5. Register Descriptions for PCA
Following are detailed descriptions of the special function registers related to the operation of the PCA.
204
Rev. 1.7