C8051F330-GMR Datasheet, PDF (110/210 Pages) Silicon Laboratories – Mixed-Signal ISP Flash MCU

C8051F330/1/2/3/4/5
SFR Definition 13.1. OSCICL: Internal H-F Oscillator Calibration
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
-
Variable
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 SFR Address:
0xB3
Bit7: UNUSED. Read = 0. Write = don’t care.
Bits 6–0: OSCICL: Internal Oscillator Calibration Register.
This register determines the internal oscillator period. When set to 0000000b, the H-F oscil-
lator operates at its fastest setting. When set to 1111111b, the H-F oscillator operates at its
slowest setting. On C8051F330/1/2/3/4/5 devices, the reset value is factory calibrated to
generate an internal oscillator frequency of 24.5 MHz.
SFR Definition 13.2. OSCICN: Internal H-F Oscillator Control
R/W
R
R
R
R
R
R/W
IOSCEN IFRDY
-
-
-
-
IFCN1
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit7:
Bit6:
Bits5–2:
Bits1–0:
IOSCEN: Internal H-F Oscillator Enable Bit.
0: Internal H-F Oscillator Disabled.
1: Internal H-F Oscillator Enabled.
IFRDY: Internal H-F Oscillator Frequency Ready Flag.
0: Internal H-F Oscillator is not running at programmed frequency.
1: Internal H-F Oscillator is running at programmed frequency.
UNUSED. Read = 0000b, Write = don't care.
IFCN1–0: Internal H-F Oscillator Frequency Control Bits.
00: SYSCLK derived from Internal H-F Oscillator divided by 8.
01: SYSCLK derived from Internal H-F Oscillator divided by 4.
10: SYSCLK derived from Internal H-F Oscillator divided by 2.
11: SYSCLK derived from Internal H-F Oscillator divided by 1.
R/W
IFCN0
Bit0
Reset Value
11000000
SFR Address:
0xB2
114
Rev. 1.7