C8051F330-GMR Datasheet, PDF (74/210 Pages) Silicon Laboratories – Mixed-Signal ISP Flash MCU

C8051F330/1/2/3/4/5
C8051F330/1
PROGRAM/DATA MEMORY
(FLASH)
0x1E00
0x1DFF
RESERVED
8 K FLASH
(In-System
Programmable in 512
Byte Sectors)
0x0000
C8051F332/3
PROGRAM/DATA MEMORY
(FLASH)
0x0FFF
4 K FLASH
(In-System
Programmable in 512
Byte Sectors)
0x0000
0xFF
0x80
0x7F
0x30
0x2F
0x20
0x1F
0x00
DATA MEMORY (RAM)
INTERNAL DATA ADDRESS SPACE
Upper 128 RAM
(Indirect Addressing
Only)
Special Function
Register's
(Direct Addressing Only)
(Direct and Indirect
Addressing)
Bit Addressable
General Purpose
Registers
Lower 128 RAM
(Direct and Indirect
Addressing)
0xFFFF
EXTERNAL DATA ADDRESS SPACE
Same 512 bytes as from
0x0000 to 0x01FF, wrapped
on 512-byte boundaries
0x0200
0x01FF
0x0000
XRAM - 512 Bytes
(accessable using MOVX
instruction)
C8051F334/5
PROGRAM/DATA MEMORY
(FLASH)
0x7FF
2 K FLASH
(In-System
Programmable in 512
Byte Sectors)
0x0000
Figure 9.2. Memory Map
9.2.1. Program Memory
The CIP-51 core has a 64 kB program memory space. The C8051F330/1 implements 8 kB of this program
memory space as in-system, re-programmable Flash memory, organized in a contiguous block from
addresses 0x0000 to 0x1DFF. Addresses above 0x1DFF are reserved on the 8 kB devices. The
C8051F332/3 and C8051F334/5 implement, in contiguous blocks, 2 and 4 kB, from addresses 0x0000 to
0x07FF or 0x0000 to 0x0FFF, respectively. Addresses above 0x0800 and 0x1000 are reserved on the 2
and 4 kB devices, respectively.
Program memory is normally assumed to be read-only. However, the CIP-51 can write to program memory
by setting the Program Store Write Enable bit (PSCTL.0) and using the MOVX write instruction. This fea-
ture provides a mechanism for the CIP-51 to update program code and use the program memory space for
non-volatile data storage. Refer to Section “11. Flash Memory” on page 103 for further details.
Rev. 1.7
77