C8051F330-GMR Datasheet, PDF (17/210 Pages) Silicon Laboratories – Mixed-Signal ISP Flash MCU

C8051F330/1/2/3/4/5
VDD
GND
RST/C2CK
Analog/Digital
Power
C2D
Debug HW
8 kB
8
FLASH
0
256 byte
5 ^Reset
SRAM
POR
Brown-
Out
1
512 byte
XRAM
XTAL1
XTAL2
External
Oscillator
Circuit
24.5 MHz (2%)
Internal
Oscillator
C
o SFR Bus
r
System Clock
e
80 kHz
Internal
Oscillator
Port 0
Latch
UART
Timer 0,
1, 2, 3
3-Chnl
PCA/
WDT
SMBus
SPI
Port 1
Latch
P
0
D
r
v
X
B
A
R
P
1
D
r
v
VREF
VDD
10-bit
200ksps
ADC
CP0 ₊
-
VREF
Temp
A
M
U
X
10-bit
DAC
AIN0-AIN15
Port 2
Latch
C2D
P0.0/VREF
P0.1/IDA0
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVSTR
P0.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0/C2D
Figure 1.1. C8051F330 Block Diagram
VDD
GND
RST/C2CK
Analog/Digital
Power
C2D
Debug HW
8 kB
8
FLASH
0
256 byte
5 ^Reset
SRAM
POR
Brown-
Out
1
512 byte
XRAM
XTAL1
XTAL2
External
Oscillator
Circuit
24.5 MHz (2%)
Internal
Oscillator
C
o SFR Bus
r
System Clock
e
80 kHz
Internal
Oscillator
Port 0
Latch
UART
Timer 0,
1, 2, 3
3-Chnl
PCA/
WDT
SMBus
SPI
Port 1
Latch
P
0
D
r
v
X
B
A
R
P
1
D
r
v
CP0 ₊
-
P0.0
P0.1
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6
P0.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
Port 2
Latch
C2D
P2.0/C2D
Figure 1.2. C8051F331 Block Diagram
Rev. 1.7
19