SI5347_16 Datasheet, PDF (9/55 Pages) Silicon Laboratories – Dual/Quad DSPLL Any-Frequency, Any-Output Jitter Attenuators

Si5347/46 Rev D Data Sheet
Functional Description
3.6.4 Input Configuration and Terminations
Each of the inputs can be configured as differential or single-ended LVCMOS. The recommended input termination schemes are shown
in the figure below. Standard 50% duty cycle signals must be ac-coupled, while low duty cycle Pulsed CMOS signals can be dc-cou-
pled. Unused inputs can be disabled and left unconnected when not in use.
Standard AC-coupled Differential LVDS
50
3.3 V, 2.5 V
50
LVDS or CML
INx
100
INxb
Si5347/46
Standard
Pulsed CMOS
3.3 V, 2.5 V
LVPECL
Standard AC-coupled Differential LVPECL
Si5347/46
50
INx
Standard
100
50
INxb
Pulsed CMOS
Standard AC-coupled Single-ended
50
3.3 V, 2.5 V, 1.8 V
LVCMOS
Si5347/46
INx
Standard
INxb
Pulsed CMOS
Pulsed CMOS DC-coupled Single-ended
3.3 V, 2.5 V, 1.8 V
LVCMOS
R1
50
INx
R2
INxb
Resistor values for
fIN_PULSED < 1 MHz
VDD R1 (Ohm) R2 (Ohm)
1.8V
324
665
2.5V
511
475
3.3V
634
365
Si5347/46
Standard
Pulsed CMOS
Figure 3.5. Termination of Differential and LVCMOS Input Signals
3.6.5 Hitless Input Switching
Hitless switching is a feature that prevents a phase offset from propagating to the output when switching between two clock inputs that
have a fixed phase relationship. A hitless switch can only occur when the two input frequencies are frequency locked, meaning that
they have to be exactly at the same frequency, or at an integer frequency relationship to each other. When hitless switching is enabled,
the DSPLL simply absorbs the phase difference between the two input clocks during an input switch. When disabled, the phase differ-
ence between the two inputs is propagated to the output at a rate determined by the DSPLL Loop Bandwidth. The hitless switching
feature supports clock frequencies down to the minimum input frequency of 8 kHz. Hitless switching can be enabled on a per DSPLL
basis.
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