SI5347_16 Datasheet, PDF (10/55 Pages) Silicon Laboratories – Dual/Quad DSPLL Any-Frequency, Any-Output Jitter Attenuators

Si5347/46 Rev D Data Sheet
Functional Description
3.6.6 Ramped Input Switching
When switching between two plesiochronous input clocks (i.e., the frequencies are "almost the same" but not quite), ramped input
switching should be enabled to ensure a smooth transition between the two inputs. Ramped input switching avoids frequency transients
and overshoot when switching between frequencies and so is the default switching mode in CBPro. The feature should be turned off
when switching between input clocks that are always frequency locked (i.e., are always the same exact frequency). The same ramp
rate settings are used for both holdover exit and clock switching. For more information on ramped exit from holdover, see 3.3.5 Hold-
over Mode.
3.6.7 Glitchless Input Switching
The DSPLLs have the ability of switching between two input clock frequencies that are up to ±500 ppm apart. The DSPLL will pull-in to
the new frequency using the DSPLL Loop Bandwidth or using the Fastlock Loop Bandwidth if it is enabled. The loss of lock (LOL) indi-
cator will assert while the DSPLL is pulling-in to the new clock frequency. There will be no output runt pulses generated at the output
during the transition.
3.6.8 Synchronizing to Gapped Input Clocks
Each of the DSPLLs support locking to an input clock that has missing periods. This is also referred to as a gapped clock. The purpose
of gapped clocking is to modulate the frequency of a periodic clock by selectively removing some of its cycles. Gapping a clock severely
increases its jitter, so a phase-locked loop with high jitter tolerance and low loop bandwidth is required to produce a low-jitter periodic
clock. The resulting output will be a periodic non-gapped clock with an average frequency of the input with its missing cycles. For exam-
ple, an input clock of 100 MHz with one cycle removed every 10 cycles will result in a 90 MHz periodic non-gapped output clock. This is
shown in the figure below.
Gapped Input Clock
100 MHz clock
1 missing period every 10
Periodic Output Clock
90 MHz non-gapped clock
100 ns
100 ns
1 2 3 4 5 6 7 8 9 10
10 ns
Period Removed
DSPLL
123456789
11.11111... ns
Figure 3.6. Generating an Averaged Clock Output Frequency from a Gapped Clock Input
A valid gapped clock input must have a minimum frequency of 10 MHz with a maximum of two missing cycles out of every 8. Locking to
a gapped clock will not trigger the LOS, OOF, and LOL fault monitors. Clock switching between gapped clocks may violate the hitless
switching specification in Table 5.8 Performance Characteristics on page 29 when the switch occurs during a gap in either input clock.
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