SI5347_16 Datasheet, PDF (25/55 Pages) Silicon Laboratories – Dual/Quad DSPLL Any-Frequency, Any-Output Jitter Attenuators

Si5347/46 Rev D Data Sheet
Electrical Specifications
Table 5.3. Input Clock Specifications
(V_DD = 1.8 V ±5%, V_DDA = 3.3 V ±5%, T_A = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Standard Input Buffer with Differential or Single-Ended/LVCMOS — AC-coupled (IN0, IN1, IN2, IN3/FB_IN)
Input Frequency Range
f_IN
Differential
0.008
—
750
All Single-ended signals
0.008
—
250
(including LVCMOS)
Voltage Swing¹
V_IN
Differential AC-coupled
100
f_IN < 250 MHz
—
1800
Differential AC-coupled
225
—
1800
250 MHz < f_IN < 750 MHz
Single-ended AC-coupled
100
—
3600
f_IN< 250 MHz
Slew Rate^2,3
SR
400
—
—
Duty Cycle
DC
40
—
60
Input Capacitance
C_IN
—
0.3
—
Input Resistance
R_IN
—
16
—
Pulsed CMOS Input Buffer — DC-coupled (IN0, IN1, IN2, IN3)⁴
Input Frequency
f_{IN_PULSED}
0.008
—
250
Input Voltage
V_IL
–0.2
—
0.4
V_IH
0.8
—
—
Slew Rate^2,3
SR
400
—
—
Duty Cycle
DC
40
—
60
Minimum Pulse Width
PW
Pulse Input
1.6
—
—
Input Resistance
R_IN
—
8
—
REFCLK (Applied to XA/XB)
REFCLK Frequency
f_{IN_REF}
Full operating range. Jitter 24.97
—
54.06
performance may be re-
duced.
Range for best jitter.
48
—
54
Input Voltage Swing
V_{IN_DIFF}
365
—
2500
V_{IN_SE}
365
—
2000
Slew rate^2,3
SR
Imposed for best jitter per-
400
—
—
formance
Input Duty Cycle
DC
40
—
60
Unit
MHz
MHz
mVpp_se
mVpp_se
mVpp_se
V/µs
%
pF
kΩ
MHz
V
V
V/µs
%
ns
kΩ
MHz
MHz
mVpp_diff
mVpp_se
V/µs
%
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