SI5347_16 Datasheet, PDF (30/55 Pages) Silicon Laboratories – Dual/Quad DSPLL Any-Frequency, Any-Output Jitter Attenuators

Si5347/46 Rev D Data Sheet
Electrical Specifications
Table 5.8. Performance Characteristics
(V_DD = 1.8 V ±5%, or 3.3 V ±5%, V_DDA = 3.3 V ±5%, T_A = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
PLL Loop Bandwidth
f_BW
Programming Range¹
0.1
—
Initial Start-Up Time
t_START
Time from power-up to
—
30
when the device gener-
ates free-running clocks
PLL Lock Time²
t_ACQ
With Fastlock enabled,
—
280
f_IN = 19.44 MHz
POR to Serial Interface Ready³
t_RDY
—
—
Jitter Peaking
J_PK
Measured with a frequen-
—
—
cy plan running a 25 MHz
input, 25 MHz output, and
a loop bandwidth of 4 Hz
Jitter Tolerance
J_TOL
Compliant with G.8262
—
Options 1&2
3180
Carrier Frequency =
10.3125 GHz
Jitter Modulation Frequen-
cy = 10 Hz
Maximum Phase
Transient During a
Hitless Switch
t_SWITCH
Only valid for a single au-
—
—
tomatic switch between
two input clocks at same
frequency
Only valid for a single
manual switch between
two input clocks at same
frequency
—
—
Pull-in Range
ω_P
—
500
Input-to-Output Delay Variation
t_IODELAY Measured between a com-
—
—
mon 2 MHz input and 2
MHz output with different
DSPLLs on the same unit.
DSPLL BW = 4 kHz
Measured between a com-
—
—
mon 2 MHz input and 2
MHz output with different
DSPLLs between units.
DSPLL BW = 4 kHz
RMS Phase Jitter⁴
J_GEN
12 kHz to 20 MHz
—
95
Max
Unit
4000
Hz
45
ms
300
ms
15
ms
0.1
dB
—
UI pk-pk
2.4
ns
1.2
ns
—
ppm
1.6
ns
1.8
ns
140
fs rms
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