SI5347_16 Datasheet, PDF (31/55 Pages) Silicon Laboratories – Dual/Quad DSPLL Any-Frequency, Any-Output Jitter Attenuators

Si5347/46 Rev D Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Notes:
1. Actual loop bandwidth might be lower; please refer to CBPro for actual value on your frequency plan.
2. Lock Time can vary significantly depending on several parameters, such as bandwidths, LOL thresholds, etc. For this case, lock
time was measured with nominal and fastlock bandwidths, both set to 100 Hz, LOL set/clear thresholds of 3/0.3 ppm respectively,
using IN0 as clock reference by removing the reference and enabling it again, then measuring the delta time between the first
rising edge of the clock reference and the LOL indicator de-assertion.
3. Measured as time from valid VDD/VDDA rails (90% of their value) to when the serial interface is ready to respond to commands.
4. Jitter generation test conditions: f_IN = 19.44 MHz, f_OUT = 156.25 MHz LVPECL, loop bandwidth = 100 Hz.
Does not include jitter from input reference.
Table 5.9. I²C Timing Specifications (SCL,SDA)
Parameter
Symbol
Test Condition
SCL Clock
f_SCL
Frequency
SMBus Timeout
—
Hold Time (repeated)
START Condition
Low Period of the SCL Clock
HIGH Period of the SCL
Clock
Set-up Time for a Repeated
START Condition
Data Hold Time
Data Set-up Time
Rise Time of Both SDA and
SCL Signals
Fall Time of Both SDA and
SCL Signals
Set-up Time for STOP Con-
dition
Bus Free Time between a
STOP and START Condition
Data Valid Time
Data Valid Acknowledge
Time
t_HD:STA
t_LOW
t_HIGH
t_SU:STA
t_HD:DAT
t_SU:DAT
t_r
t_f
t_SU:STO
t_BUF
t_VD:DAT
t_VD:ACK
When Timeout is
Enabled
Standard Mode
Fast Mode
Unit
100 kbps
400 kbps
Min
Max
Min
Max
—
100
—
400
kHz
25
35
25
35
ms
4.0
—
0.6
—
µs
4.7
—
1.3
—
µs
4.0
—
0.6
—
µs
4.7
—
0.6
—
µs
100
—
100
—
ns
250
—
100
—
ns
—
1000
20
300
ns
—
300
—
300
ns
4.0
—
0.6
—
µs
4.7
—
1.3
—
µs
—
3.45
—
0.9
µs
—
3.45
—
0.9
µs
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