SI5347_16 Datasheet, PDF (5/55 Pages) Silicon Laboratories – Dual/Quad DSPLL Any-Frequency, Any-Output Jitter Attenuators

Si5347/46 Rev D Data Sheet
Functional Description
No valid input
clocks available
for selection
Power-Up
Reset and
Initialization
No valid
input clocks
selected
An input is
qualified and
available for
selection
Holdover
Mode
Free-run
Valid input clock
selected
Lock Acquisition
(Fast Lock)
Phase lock on
selected input
clock is achieved
Input Clock
Switch
Yes
No
Holdover
History
Valid?
Locked
Mode
Selected input
clock fails
Yes _{Other Valid}
Clock Inputs
No ^Available?
Figure 3.1. Modes of Operation
3.3.2 Free-run Mode
Once power is applied to the Si5347 and initialization is complete, all four DSPLLs will automatically enter Free-run Mode. The frequen-
cy accuracy of the generated output clocks in Free-run Mode is entirely dependent on the frequency accuracy of the external crystal or
reference clock on the XA/XB pins. For example, if the crystal frequency is ±100 ppm, then all the output clocks will be generated at
their configured frequency ±100 ppm in Free-run Mode. Any drift of the crystal frequency will be tracked at the output clock frequencies.
A TCXO or OCXO is recommended for applications that need better frequency accuracy and stability while in Free-run Mode or Hold-
over Mode.
3.3.3 Lock Acquisition Mode
Each of the DSPLLs independently monitors its configured inputs for a valid clock. If at least one valid clock is available for synchroni-
zation, a DSPLL will automatically start the lock acquisition process.
If the fast lock feature is enabled, a DSPLL will acquire lock using the Fastlock Loop Bandwidth setting and then transition to the DSPLL
Loop Bandwidth setting when lock acquisition is complete. During lock acquisition the outputs will generate a clock that follows the VCO
frequency change as it pulls-in to the input clock frequency.
3.3.4 Locked Mode
Once locked, a DSPLL will generate output clocks that are both frequency and phase locked to their selected input clocks. At this point,
any XTAL frequency drift will not affect the output frequency. Each DSPLL has its own LOLb pin and status bit to indicate when lock is
achieved. See 3.7.4 LOL Detection for more details on the operation of the loss of lock circuit.
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