SI5347_16 Datasheet, PDF (45/55 Pages) Silicon Laboratories – Dual/Quad DSPLL Any-Frequency, Any-Output Jitter Attenuators

Si5347/46 Rev D Data Sheet
Pin Descriptions
Pin
Name
Pin Number
Si5347A/B Si5347C/D
Si5346
Pin
Type²
Function
NC
28
28
22
—
No Connect. These pins are not connected to the die.
Leave disconnected.
Power
VDD
32
32
21
46
46
32
60
60
39
P
Core Supply Voltage. The device core operates from a
1.8 V supply. See the Si5347/46 Family Reference Manual
for power supply filtering recommendations. A 0402 1 µF
capacitor should be placed very near each of these pins.
—
—
40
VDDA
13
13
8
—
—
9
P
Core Supply Voltage 3.3 V. This core supply pin requires
a 3.3 V power source. See the Si5347/46 Family Refer-
P
ence Manual for power supply filtering recommendations.
A 0402 1 µF capacitor should be placed very near each of
these pins.
VDDS
40
40
26
P
Status Output Voltage. The voltage on this pin deter-
mines VOL/VOH on the Si5346 LOL_Ab and LOL_Bb out-
puts. On the Si5347, this pin determines VIL/VIH for the
FDEC and OE1b inputs. Connect to either 3.3 V or 1.8 V.
A 0.1 µF bypass capacitor should be placed very close to
this pin.
VDDO0
22
22
18
VDDO1
29
36
23
VDDO2
33
43
29
VDDO3
36
49
34
VDDO4
43
—
—
VDDO5
49
—
—
P
Output Clock Supply Voltage 0–7. Supply voltage (3.3
V, 2.5 V, 1.8 V) for OUTn, OUTnb outputs. A 0.1 uF by-
P
pass capacitor should be placed very close to this pin.
P
Leave VDDO pins of unused output drivers unconnected.
An alternate option is to connect the VDDO pin to a power
P
supply and disable the output driver to minimize current
consumption. A 0402 1 µF capacitor should be placed
P
very near each of these pins.
P
VDDO6
52
—
—
P
VDDO7
57
—
—
P
GND PAD
—
—
—
P
Ground Pad. This pad provides connection to ground and
must be connected for proper operation. Use as many vias
as practical and keep the via length to an internal ground
plan as short as possible.
Notes:
1. Refer to the Si5347/46 Family Reference Manual for more information on register setting names.
2. I = Input, O = Output, P = Power.
3. The IO_VDD_SEL control bit (0x0943 bit 0) selects 3.3 V or 1.8 V operation.
4. The voltage on the VDDS pin(s) determines 3.3 V or 1.8 V operation.
5. All status pins except I2C and SPI are push-pull.
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