SI5347_16 Datasheet, PDF (18/55 Pages) Silicon Laboratories – Dual/Quad DSPLL Any-Frequency, Any-Output Jitter Attenuators

Si5347/46 Rev D Data Sheet
Functional Description
3.8.5 Programmable Common Mode Voltage For Differential Outputs
The common mode voltage (V_CM) for the differential modes is programmable in 100 mV increments from 0.7 V to 2.3 V depending on
the voltage available at the output’s VDDO pin. Setting the common mode voltage is useful when dc-coupling the output drivers.
3.8.6 LVCMOS Output Impedance Selection
Each LVCMOS driver has a configurable output impedance to accommodate different trace impedances and drive strengths. A source
termination resistor is recommended to help match the selected output impedance to the trace impedance. There are three programma-
ble output impedance selections for each VDDO option, as shown in the table below. Note that selecting a lower source impedance
may result in higher output power consumption.
Table 3.1. Typical Output Impedance (Z_S)
VDDO
3.3 V
2.5 V
1.8 V
OUTx_CMOS_DRV = 1
38 Ω
43 Ω
—
CMOS_DRIVE_Selection
OUTx_CMOS_DRV = 2
30 Ω
35 Ω
46 Ω
OUTx_CMOS_DRV = 3
22 Ω
24 Ω
31 Ω
3.8.7 LVCMOS Output Signal Swing
The signal swing (V_OL/V_OH) of the LVCMOS output drivers is set by the voltage on the VDDO pins. Each output driver has its own
VDDO pin allowing a unique output voltage swing for each of the LVCMOS drivers.
3.8.8 LVCMOS Output Polarity
When a driver is configured as an LVCMOS output, it generates a clock signal on both pins (OUTx and OUTxb). By default the clock on
the OUTxb pin is generated with the same polarity (in phase) with the clock on the OUTx pin. The polarity of these clocks is configura-
ble, which enables complementary clock generation and/or inverted polarity with respect to other output drivers.
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