SI5347_16 Datasheet, PDF (32/55 Pages) Silicon Laboratories – Dual/Quad DSPLL Any-Frequency, Any-Output Jitter Attenuators

Si5347/46 Rev D Data Sheet
Electrical Specifications
Figure 5.1. I²C Serial Port Timing Standard and Fast Modes
Table 5.10. SPI Timing Specifications (4-Wire)
(V_DD = 1.8 V ±5%, V_DDA = 3.3 V ±5%, T_A = –40 to 85 °C)
Parameter
SCLK Frequency
SCLK Duty Cycle
SCLK Period
Delay Time, SCLK Fall to SDO Active
Delay Time, SCLK Fall to SDO
Delay Time, CSb Rise to SDO Tri-State
Setup Time, CSb to SCLK
Hold Time, SCLK Fall to CSb
Setup Time, SDI to SCLK Rise
Hold Time, SDI to SCLK Rise
Delay Time Between Chip Selects (CSb)
Symbol
Min
Typ
Max
f_SPI
—
—
20
T_DC
40
—
60
T_C
50
—
—
T_D1
—
—
18
T_D2
—
—
15
T_D3
—
—
15
T_SU1
5
—
—
T_H1
5
—
—
T_SU2
5
—
—
T_H2
5
—
—
T_CS
2
—
—
Unit
MHz
%
ns
ns
ns
ns
ns
ns
ns
ns
T_C
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