SI5347_16 Datasheet, PDF (19/55 Pages) Silicon Laboratories – Dual/Quad DSPLL Any-Frequency, Any-Output Jitter Attenuators

Si5347/46 Rev D Data Sheet
Functional Description
3.8.9 Output Enable/Disable
The Si5347/46 allows enabling/disabling outputs by pin or register control, or a combination of both. Two output enable pins are availa-
ble (OE0b, OE1b). The output enable pins can be mapped to any of the outputs (OUTx) through register configuration. By default OE0b
controls all of the outputs while OE1b remains unmapped and has no effect until configured. The figure below shows an example of an
output enable mapping scheme that is register configurable and can be stored in NVM as the default at power-up.
Enabling and disabling outputs can also be controlled by register control. This allows disabling one or more output when the OEb pin(s)
has them enabled. By default the output enable register settings are configured to allow the OEb pins to have full control.
DSPLL
A
Output
Crosspoint
Si5346
A
B
÷R0
OUT0
OUT0b
DSPLL
A
Output
Crosspoint
Si5346
A
B
÷R0
OUT0
OUT0b
DSPLL
B
A
B
÷R1
A
B
÷R2
A
B
÷R3
OUT1
OUT1b
OUT2
OUT2b
OUT3
OUT3b
OE0b
OE1b
In its default state the OE0b pin enables/disables all outputs.
The OE1b pin is not mapped and has no effect on outputs.
A
B
÷R1
OUT1
OUT1b
OE0b
DSPLL
B
A
B
÷R2
OUT2
OUT2b
A
B
÷R3
OUT3
OUT3b
OE1b
An example of a configurable output enable scheme. In this
case OE0b controls the outputs associated with DSPLL A,
while OE1b controls the outputs of DSPLL B.
Figure 3.17. Example of Configuring Output Enable Pins
3.8.10 Output Disable During LOL
By default a DSPLL that is out of lock will generate either free-running clocks or generate clocks in holdover mode. There is an option to
disable the outputs when a DSPLL is LOL. This option can be useful to force a downstream PLL into holdover.
3.8.11 Output Disable During XAXB_LOS
The internal oscillator circuit (OSC) in combination with the external crystal (XTAL) provides a critical function for the operation of the
DSPLLs. In the event of a crystal failure the device will assert an XAXB_LOS alarm. By default all outputs will be disabled during asser-
tion of the XAXB_LOS alarm. There is an option to leave the outputs enabled during an XAXB_LOS alarm, but the frequency accuracy
and stability will be indeterminate during this fault condition.
3.8.12 Output Driver State When Disabled
The disabled state of an output driver is register configurable as disable low or disable high.
3.8.13 Synchronous/Asynchronous Output Disable
Outputs can be configured to disable synchronously or asynchronously. In synchronous disable mode the output will wait until a clock
period has completed before the driver is disabled. This prevents unwanted runt pulses from occurring when disabling an output. In
asynchronous disable mode, the output clock will disable immediately without waiting for the period to complete.
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